HT46R94 datasheet(35/62 Pages) HOLTEK

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HT46R94

Rev. 1.10

November 5, 2008

Interrupt Operation

A Timer/Event Counter overflow, a Time Base overflow,

an end of A/D conversion or the external interrupt line

being pulled low will all generate an interrupt request by

setting their corresponding request flag, if their appropri-

ate interrupt enable bit is set. When this happens, the

Program Counter, which stores the address of the next

instruction to be executed, will be transferred onto the

stack. The Program Counter will then be loaded with a

new address which will be the value of the correspond-

ing interrupt vector. The microcontroller will then fetch its

next instruction from this interrupt vector. The instruction

at this vector will usually be a JMP statement which will

jump to another section of program which is known as

the interrupt service routine. Here is located the code to

control the appropriate interrupt. The interrupt service

routine must be terminated with a RETI statement,

which retrieves the original Program Counter address

from the stack and allows the microcontroller to continue

with normal execution at the point where the interrupt

occurred.

The various interrupt enable bits, together with their as-

sociated request flags, are shown in the following dia-

gram with their order of priority.

Once an interrupt subroutine is serviced, all the other in-

terrupts will be blocked, as the EMI bit will be cleared au-

tomatically. This will prevent any further interrupt nesting

from occurring. However, if other interrupt requests oc-

cur during this interval, although the interrupt will not be

immediately serviced, the request flag will still be re-

corded. If an interrupt requires immediate servicing

while the program is already in another interrupt service

routine, the EMI bit should be set after entering the rou-

tine, to allow interrupt nesting. If the stack is full, the in-

terrupt request will not be acknowledged, even if the

related interrupt is enabled, until the Stack Pointer is

decremented. If immediate service is desired, the stack

must be prevented from becoming full.

Interrupt Priority

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In case of simultaneous requests, the

following table shows the priority that is applied. These

can be masked by resetting the EMI bit.

Interrupt Source

Vector

Priority

External Interrupt

04H

Timer/Event Counter 0 Overflow

08H

Timer/Event Counter 1 Overflow

0CH

Time Base Overflow

10H

A/D Converter Conversion End

14H

Interrupt Priority

In cases where both external and internal interrupts are

enabled and where an external and internal interrupt oc-

curs simultaneously, the external interrupt will always

have priority and will therefore be serviced first. Suitable

masking of the individual interrupts using the INTC0 and

INTC1 registers can prevent simultaneous occurrences.

External Interrupt

For an external interrupt to occur, the global interrupt en-

able bit, EMI, and external interrupt enable bit, EEI, must

first be set. An actual external interrupt will take place

when the external interrupt request flag, EIF in INTC0. As

the external interrupt is a dual edge triggered type, the

EIF flag will be set when either a high to low or low to high

transition appears on the INT line. The external interrupt

pin is pin-shared with the output pin PD0 and can only be

configured as an external interrupt pin if the correspond-

ing external interrupt enable bit in the INTC0 register has

been set and the PD0 output is disabled by setting the

LCDEN bit in the LCDC register to zero and the PD0 bit

set high. If the external interrupt enable bit is not set then

the pin can be used as a PD0 CMOS output pin. When

the interrupt is enabled, the stack is not full and a high to

A u t o m a t i c a l l y C l e a r e d b y I S R

M a n u a l l y S e t o r C l e a r e d b y S o f t w a r e

E x t e r n a l I n t e r r u p t

R e q u e s t F l a g E I F

E E I

E M I

P r i o r i t y

I n t e r r u p t

P o l l i n g

H i g h

A u t o m a t i c a l l y D i s a b l e d b y I S R

C a n b e E n a b l e d M a n u a l l y

T i m e r / E v e n t C o u n t e r 0

I n t e r r u p t R e q u e s t F l a g T 0 F

E T 0 I

L o w

E T B I

T i m e B a s e

I n t e r r u p t R e q u e s t F l a g T B F

T i m e r / E v e n t C o u n t e r 1

I n t e r r u p t R e q u e s t F l a g T 1 F

E T 1 I

E A D I

A / D C o n v e r t e r

I n t e r r u p t R e q u e s t F l a g A D F

Interrupt Structure

HT46R94 Datasheet(PDF) 35 Page - Holtek Semiconductor Inc

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