HT46R94 datasheet(43/62 Pages) HOLTEK

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HT46R94

Rev. 1.10

November 5, 2008

Watchdog Timer

The Watchdog Timer is provided to prevent program mal-

functions or sequences from jumping to unknown loca-

tions, due to certain uncontrollable external events such

as electrical noise. It operates by providing a device reset

when the WDT counter overflows. The WDT clock is sup-

plied by one of three sources selected by configuration

option: its own self contained dedicated internal WDT os-

cillator, fSYS/4 or the RTC oscillator. Note that if the WDT

configuration option has been disabled, then any instruc-

tion relating to its operation will result in no operation.

In the device, all Watchdog Timer options, such as en-

able/disable, WDT clock source and clear instruction

type all selected through configuration options. There

are no internal registers associated with the WDT in the

Cost-Effective A/D Type MCU series. One of the WDT

clock sources is an internal oscillator which has an ap-

proximate period of 65

ms at a supply voltage of 5V. How-

ever, it should be noted that this specified internal clock

period can vary with VDD, temperature and process

variations. Watchdog Timer time-out value is of 2

14/f

S to

21/f

If the fSYS/4 clock is used as the WDT clock source, it

should be noted that when the system enters the Power

Down Mode, then the instruction clock is stopped and

the WDT will lose its protecting purposes. For systems

that operate in noisy environments, using the internal

WDT oscillator is strongly recommended.

Under normal program operation, a WDT time-out will

initialise a device reset and set the status bit TO. How-

ever, if the system is in the Power Down Mode, when a

WDT time-out occurs, the TO bit in the status register

will be set and only the Program Counter and Stack

Pointer will be reset. Three methods can be adopted to

clear the contents of the WDT. The first is an external

hardware reset, which means a low level on the RES

pin, the second is using the watchdog software instruc-

tions and the third is via a

²HALT² instruction.

There are two methods of using software instructions to

clear the Watchdog Timer, one of which must be chosen

by configuration option. The first option is to use the sin-

gle

²CLR WDT² instruction while the second is to use the

two commands

²CLR WDT1² and ²CLR WDT2². For the

first option, a simple execution of

²CLR WDT² will clear

the WDT while for the second option, both

²CLR WDT1²

and

²CLR WDT2² must both be executed to successfully

clear the WDT. Note that for this second option, if

²CLR

WDT1

² is used to clear the WDT, successive executions

of this instruction will have no effect, only the execution of

²CLR WDT2² instruction will clear the WDT. Similarly

after the

²CLR WDT2² instruction has been executed,

only a successive

²CLR WDT1² instruction can clear the

Watchdog Timer.

Buzzer

Operating in a similar way to the Programmable Fre-

quency Divider, the Buzzer function provides a means of

producing a variable frequency output, suitable for ap-

plications such as Piezo-buzzer driving or other external

circuits that require a precise frequency generator. The

BZ and BZ pins form a complimentary pair, and are

pin-shared with I/O pins, PA0 and PA1. A configuration

option is used to select from one of three buzzer options.

The first option is for both pins PA0 and PA1 to be used

as normal I/Os, the second option is for both pins to be

configured as BZ and BZ buzzer pins, the third option

selects only the PA0 pin to be used as a BZ buzzer pin

with the PA1 pin retaining its normal I/O pin function.

Note that the BZ pin is the inverse of the BZ pin which to-

gether generate a differential output which can supply

more power to connected interfaces such as buzzers.

The buzzer is driven by the internal clock source, fS,

whch is then passed through a divider, the division ratio

of which is selected by configuration options to provide a

range of buzzer frequencies from fS/2 to fS/2

4. The clock

source that generates fS, which in turn controls the

buzzer frequency, can originate from three different

sources, the RTC oscillator, the WDT oscillator or the

System oscillator/4, the choice of which is determined

by the fS clock source configuration option. It is impor-

tant to note that if the RTC oscillator is selected as the

system clock, then fS and correspondingly the buzzer,

will also have the RTC oscillator as its clock source.

Note that the buzzer frequency is controlled by configu-

ration options, which select both the source clock for the

internal clock fS and the internal division ratio. There are

no internal registers associated with the buzzer fre-

quency.

If the configuration options have selected both pins PA0

and PA1 to function as a BZ and BZ complementary pair

of buzzer outputs, then for correct buzzer operation it is

essential that both pins must be setup as outputs by set-

ting bits PAC0 and PAC1 of the PAC port control register

to zero. The PA0 data bit in the PA data register must

also be set high to enable the buzzer outputs, if set low,

¸ 1 6

8 - S t a g e P r e s c a l e r

8 - t o - 1 M U X

W D T T i m e - o u t

P 0 S C 2 ~ P 0 S C 0

O p t i o n

S e l e c t

f S Y S / 4

W D T O S C

R T C O S C

9 - B i t C o u n t e r

f S

Watchdog Timer

HT46R94 Datasheet(PDF) 43 Page - Holtek Semiconductor Inc

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