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Data Sheet

ADF4351

Rev. 0 | Page 11 of 28

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 16. The SW1 and

SW2 switches are normally closed. The SW3 switch is normally

open. When power-down is initiated, SW3 is closed, and SW1

and SW2 are opened. In this way, no loading of the REFIN pin

occurs during power-down.

BUFFER

TO R COUNTER

REFIN

100k

Ω

SW2

SW3

SW1

POWER-DOWN

CONTROL

Figure 16. Reference Input Stage

RF N DIVIDER

The RF N divider allows a division ratio in the PLL feedback

path. The division ratio is determined by the INT, FRAC, and

MOD values, which build up this divider (see Figure 17).

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

MOD

VALUE

FRAC

VALUE

INT

VALUE

RF N DIVIDER

N = INT + FRAC/MOD

FROM

VCO OUTPUT/

OUTPUT DIVIDERS

TO PFD

N COUNTER

Figure 17. RF N Divider

INT, FRAC, MOD, and R Counter Relationship

The INT, FRAC, and MOD values, in conjunction with the

R counter, make it possible to generate output frequencies that

are spaced by fractions of the PFD frequency. For more informa-

tion, see the RF Synthesizer—A Worked Example section.

The RF VCO frequency (RFOUT) equation is

RFOUT = fPFD × (INT + (FRAC/MOD))

(1)

where:

RFOUT is the output frequency of the voltage controlled oscillator

(VCO).

INT is the preset divide ratio of the binary 16-bit counter (23 to

65,535 for the 4/5 prescaler; 75 to 65,535 for the 8/9 prescaler).

FRAC is the numerator of the fractional division (0 to MOD − 1).

MOD is the preset fractional modulus (2 to 4095).

The PFD frequency (fPFD) equation is

fPFD = REFIN × [(1 + D)/(R × (1 + T))]

(2)

where:

REFIN is the reference input frequency.

D is the REFIN doubler bit (0 or 1).

R is the preset divide ratio of the binary 10-bit programmable

reference counter (1 to 1023).

T is the REFIN divide-by-2 bit (0 or 1).

Integer-N Mode

If FRAC = 0 and the DB8 (LDF) bit in Register 2 is set to 1, the

synthesizer operates in integer-N mode. The DB8 bit in Register 2

should be set to 1 for integer-N digital lock detect.

R Counter

The 10-bit R counter allows the input reference frequency

(REFIN) to be divided down to produce the reference clock

to the PFD. Division ratios from 1 to 1023 are allowed.

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

The phase frequency detector (PFD) takes inputs from the

R counter and N counter and produces an output proportional

to the phase and frequency difference between them. Figure 18

is a simplified schematic of the phase frequency detector.

CLR2

DOWN

HIGH

CPOUT

–IN

+IN

CHARGE

PUMP

DELAY

CLR1

Figure 18. PFD Simplified Schematic

The PFD includes a programmable delay element that sets the

width of the antibacklash pulse (ABP). This pulse ensures that

there is no dead zone in the PFD transfer function. Bit DB22 in

•

When Bit DB22 is set to 0, the ABP width is programmed to

6 ns, the recommended value for fractional-N applications.

•

When Bit DB22 is set to 1, the ABP width is programmed to

3 ns, the recommended value for integer-N applications.

For integer-N applications, the in-band phase noise is improved

by enabling the shorter pulse width. The PFD frequency can

operate up to 90 MHz in this mode. To operate with PFD

frequencies higher than 45 MHz, VCO band select must be dis-

abled by setting the phase adjust bit (DB28) to 1 in Register 1.

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