ADF4351 datasheet(22/28 Pages) AD

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ADF4351

Data Sheet

Rev. 0 | Page 22 of 28

It is important that the PFD frequency remain constant (in this

example, 13 MHz). This allows the user to design one loop filter

for both setups without encountering stability issues. Note that

the ratio of the RF frequency to the PFD frequency principally

affects the loop filter design, not the actual channel spacing.

CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES

As described in the Low Noise and Low Spur Modes section, the

ADF4351 contains a number of features that allow optimization

for noise performance. However, in fast-locking applications,

the loop bandwidth generally needs to be wide and, therefore,

the filter does not provide much attenuation of the spurs. If the

cycle slip reduction feature is enabled, the narrow loop band-

width is maintained for spur attenuation, but faster lock times

are still possible.

Cycle Slips

Cycle slips occur in integer-N/fractional-N synthesizers when

the loop bandwidth is narrow compared to the PFD frequency.

The phase error at the PFD inputs accumulates too fast for the

PLL to correct, and the charge pump temporarily pumps in the

wrong direction. This slows down the lock time dramatically.

The ADF4351 contains a cycle slip reduction feature that

extends the linear range of the PFD, allowing faster lock times

without modifications to the loop filter circuitry.

When the circuitry detects that a cycle slip is about to occur, it

turns on an extra charge pump current cell. This cell outputs a

constant current to the loop filter or removes a constant current

from the loop filter (depending on whether the VCO tuning

voltage needs to increase or decrease to acquire the new

frequency). The effect is that the linear range of the PFD is

increased. Loop stability is maintained because the current is

constant and is not a pulsed current.

If the phase error increases again to a point where another cycle

slip is likely, the ADF4351 turns on another charge pump cell.

This continues until the ADF4351 detects that the VCO fre-

quency has exceeded the desired frequency. The extra charge

pump cells are turned off one by one until all the extra charge

pump cells are disabled and the frequency settles to the original

loop filter bandwidth.

Up to seven extra charge pump cells can be turned on. In most

applications, seven cells are enough to eliminate cycle slips

altogether, providing much faster lock times.

Setting Bit DB18 in Register 3 to 1 enables cycle slip reduction.

Note that the PFD requires a 45% to 55% duty cycle for CSR to

operate correctly. If the REFIN frequency does not have a suitable

duty cycle, enabling the RDIV2 mode (Bit DB24 in Register 2)

ensures that the input to the PFD has a 50% duty cycle.

SPURIOUS OPTIMIZATION AND FAST LOCK

Narrow loop bandwidths can filter unwanted spurious signals,

but these bandwidths usually have a long lock time. A wider

loop bandwidth achieves faster lock times but may lead to

increased spurious signals inside the loop bandwidth.

The fast lock feature can achieve the same fast lock time as the

wider bandwidth but with the advantage of a narrow final loop

bandwidth to keep spurs low.

FAST LOCK TIMER AND REGISTER SEQUENCES

If the fast lock mode is used, a timer value must be loaded into

the PLL to determine the duration of the wide bandwidth mode.

When Bits[DB16:DB15] in Register 3 are set to 01 (fast lock

enable), the timer value is loaded by the 12-bit clock divider

value (Bits[DB14:DB3] in Register 3). The following sequence

must be programmed to use fast lock:

1. Start the initialization sequence (see the Register Initialization

Sequence section). This sequence occurs only once after

powering up the part.

2. Load Register 3 by setting Bits[DB16:DB15] to 01 and by

setting the selected fast lock timer value (Bits[DB14:DB3]).

The duration that the PLL remains in wide bandwidth mode

is equal to the fast lock timer/fPFD.

FAST LOCK EXAMPLE

If a PLL has a reference frequency of 13 MHz, fPFD of 13 MHz,

and a required lock time of 60 µs, the PLL is set to wide bandwidth

mode for 20 µs. This example assumes a modulus of 65 for channel

spacing of 200 kHz. The VCO calibration time of 20 µs must also

be taken into account (achieved by programming the higher band

select clock mode using Bit DB23 of Register 3).

If the time set for the PLL lock time in wide bandwidth mode is

20 µs, then

Fast Lock Timer Value = (VCO Band Select Time +

PLL Lock Time in Wide Bandwidth) × fPFD/MOD

Fast Lock Timer Value = (20 µs + 20 µs) × 13 MHz/65 = 8

Therefore, a value of 8 must be loaded into the clock divider

value in Register 3 (see Step 2 in the Fast Lock Timer and

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