ADF4351 datasheet(3/28 Pages) AD

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Data Sheet

ADF4351

Rev. 0 | Page 3 of 28

SPECIFICATIONS

AVDD = DVDD = VVCO = SDVDD = VP = 3.3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Operating

temperature range is −40°C to +85°C.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

REF

IN CHARACTERISTICS

Input Frequency

250

MHz

For f < 10 MHz, ensure slew rate > 21 V/µs

Input Sensitivity

0.7

V p-p

Biased at AV

DD/2; ac coupling ensures AVDD/2 bias

Input Capacitance

Input Current

±60

µA

PHASE FREQUENCY DETECTOR (PFD)

Phase Detector Frequency

MHz

Fractional-N

MHz

Integer-N (band select enabled)

MHz

Integer-N (band select disabled)

CHARGE PUMP

CP Sink/Source

SET = 5.1 kΩ

High Value

Low Value

0.312

SET Range

3.9

kΩ

Sink and Source Current Matching

0.5 V ≤ V

CP ≤ 2.5 V

CP vs. VCP

1.5

0.5 V ≤ V

CP ≤ 2.5 V

CP vs. Temperature

CP = 2.0 V

LOGIC INPUTS

Input High Voltage, V

INH

1.5

Input Low Voltage, V

INL

0.6

Input Current, I

INH/IINL

±1

µA

Input Capacitance, C

3.0

LOGIC OUTPUTS

Output High Voltage, V

DD − 0.4

CMOS output selected

Output High Current, I

500

µA

Output Low Voltage, V

0.4

OL = 500 µA

POWER SUPPLIES

3.0

3.6

DD, VVCO, SDVDD, VP

These voltages must equal AV

DD + AIDD

Output Dividers

6 to 36

Each output divide-by-2 consumes 6 mA

VCO

RFOUT

RF output stage is programmable

Low Power Sleep Mode

µA

RF OUTPUT CHARACTERISTICS

VCO Output Frequency

2200

4400

MHz

Fundamental VCO mode

Minimum VCO Output Frequency

Using Dividers

34.375

MHz

2200 MHz fundamental output and

divide-by-64 selected

VCO Sensitivity, K

MHz/V

Frequency Pushing (Open-Loop)

MHz/V

Frequency Pulling (Open-Loop)

kHz

Into 2.00 VSWR load

Harmonic Content (Second)

−19

dBc

Fundamental VCO output

−20

dBc

Divided VCO output

Harmonic Content (Third)

−13

dBc

Fundamental VCO output

−10

dBc

Divided VCO output

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