ADF4351 datasheet(23/28 Pages) AD

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Data Sheet

ADF4351

Rev. 0 | Page 23 of 28

FAST LOCK LOOP FILTER TOPOLOGY

To use fast lock mode, the damping resistor in the loop filter is

reduced to one-fourth its value while in wide bandwidth mode.

To achieve the wider loop filter bandwidth, the charge pump

current increases by a factor of 16; to maintain loop stability,

the damping resistor must be reduced by a factor of one-fourth.

To enable fast lock, the SW pin is shorted to the AGND pin by

setting Bits[DB16:DB15] in Register 3 to 01. The following two

topologies are available:



The damping resistor (R1) is divided into two values

(R1 and R1A) that have a ratio of 1:3 (see Figure 31).



An extra resistor (R1A) is connected directly from SW, as

shown in Figure 32. The extra resistor is calculated such

that the parallel combination of the extra resistor and the

damping resistor (R1) is reduced to one-fourth the original

value of R1 (see Figure 32).

ADF4351

CPOUT

R1A

VCO

Figure 31. Fast Lock Loop Filter Topology 1

ADF4351

CPOUT

R1A

VCO

Figure 32. Fast Lock Loop Filter Topology 2

SPUR MECHANISMS

This section describes the three different spur mechanisms that

arise with a fractional-N synthesizer and how to minimize them

in the ADF4351.

Fractional Spurs

The fractional interpolator in the ADF4351 is a third-order

Σ-Δ modulator with a modulus (MOD) that is programmable

to any integer value from 2 to 4095. In low spur mode (dither

on), the minimum allowable value of MOD is 50. The Σ-Δ

modulator is clocked at the PFD reference rate (fPFD), which

allows PLL output frequencies to be synthesized at a channel

step resolution of fPFD/MOD.

In low noise mode (dither off), the quantization noise from the

Σ-Δ modulator appears as fractional spurs. The interval between

spurs is fPFD/L, where L is the repeat length of the code sequence

in the digital Σ-Δ modulator. For the third-order Σ-Δ modulator

used in the ADF4351, the repeat length depends on the value of

MOD (see Table 7).

Table 7. Fractional Spurs with Dither Off (Low Noise Mode)

MOD Value (Dither Off)

Repeat

Length

Spur Interval

MOD is divisible by 2, but not by 3

2 × MOD

Channel step/2

MOD is divisible by 3, but not by 2

3 × MOD

Channel step/3

MOD is divisible by 6

6 × MOD

Channel step/6

MOD is not divisible by 2, 3, or 6

MOD

Channel step

In low spur mode (dither on), the repeat length is extended

to 221 cycles, regardless of the value of MOD, which makes the

quantization error spectrum look like broadband noise. This

may degrade the in-band phase noise at the PLL output by as

much as 10 dB. For lowest noise, dither off is a better choice,

particularly when the final loop bandwidth is low enough to

attenuate even the lowest frequency fractional spur.

Integer Boundary Spurs

Another mechanism for fractional spur creation is the inter-

actions between the RF VCO frequency and the reference

frequency. When these frequencies are not integer related (the

purpose of a fractional-N synthesizer), spur sidebands appear

on the VCO output spectrum at an offset frequency that corre-

sponds to the beat note, or difference frequency, between an

integer multiple of the reference and the VCO frequency. These

spurs are attenuated by the loop filter and are more noticeable

on channels close to integer multiples of the reference, where

the difference frequency can be inside the loop bandwidth (thus

the name integer boundary spurs).

Reference Spurs

Reference spurs are generally not a problem in fractional-N

synthesizers because the reference offset is far outside the loop

bandwidth. However, any reference feedthrough mechanism

that bypasses the loop may cause a problem. Feedthrough of

low levels of on-chip reference switching noise, coupling to the

VCO, can result in reference spur levels as high as −80 dBc. The

PCB layout must ensure adequate isolation between VCO circuitry

and the input reference to avoid a possible feedthrough path on

the board.

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