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SN11113 Datasheet(PDF) 18 Page - SONiX Technology Company

Part # SN11113
Description  USB AUDIO CONTROLLER
PDF  22 Pages
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Manufacturer  SONIX [SONiX Technology Company]
Direct Link  http://www.sonix.com.tw
Logo SONIX - SONiX Technology Company

SN11113 Datasheet(HTML) 18 Page - SONiX Technology Company

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SN11113 spec
18
Appendix A
Two wire series bus in SN11113
To provide extension capability, SN11113 contains a two wire series bus circuitry as an interface
to MCU.
The two wire series bus serves as a slave device with bit rate up to 400Kbps (fast
mode).
MCU can write two bytes to SN11113 with 8-bit register address 8’bxxxxxxx0 and
8’bxxxxxxx1; where ‘x’ means either ‘0’ or ‘1’.
MCU can also read one byte from SN11113 by
any register address.
The 7-bit slave address of SN11113 is assigned as 7’b0111000.
With ‘HIDEN’ activated, SN11113 will transfer the two bytes to the USB host via an additional
interrupt pipe when any byte is written to it by MCU.
Accompany with the two bytes two wire
series bus data, SN11113 will also send one byte of button status.
The sequence of the upward
HID report is the button status first (LSB), then register with address 8’bxxxxxx0, then register
with address 8’bxxxxxx1 (MSB).
The USB host will keep polling the upward HID report every
32mS.
When there is any button pressed or released, or two wire series bus data coming,
SN11113 will transfer the three bytes of HID report to the USB host.
SN11113 can also transfer one byte data from the USB host to its register when ‘HIDEN’ is
active.
This is accomplished by a ‘Set Output Report’ HID class request via default control
pipe.
MCU can get this downward byte by polling.
That is, MCU should read the byte at its
favorite rate.
This document just provides simple description of the two wire series bus.
User can get more
detailed explanation from the specification.
SN11113 has one input pin ‘SCL’ where it gets two wire series bus clock from MCU, and one
open-drain output pin ‘SDA’ where it sends or receives serial signal to/from MCU.
As shown
below, ‘SDA’ should be stable when ‘SCL’ is high, and can have transition only when ‘SCL’ is
low.



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