RM48L540 datasheet(6/152 Pages) TI1

6 / 152 page

RM48L940

RM48L740

RM48L540

SPNS175

– SEPTEMBER 2011

www.ti.com

RM48Lx40 16/32-Bit RISC Flash Microcontroller

4.6

Clocks

.............................................. 56

............................................................... 1

4.7

Clock Monitoring

.................................... 64

1.1

Features

.............................................. 1

4.8

Glitch Filters

........................................ 66

1.2

Applications

.......................................... 2

4.9

Device Memory Map

................................ 67

4.10

Flash Memory

...................................... 74

1.3

Description

........................................... 3

4.11

Tightly-Coupled RAM Interface Module

............ 77

1.4

Functional Block Diagram

............................ 5

4.12

Parity Protection for Accesses to peripheral RAMs

1.1

Device Configuration

................................. 7

...................................................... 77

Device Package and Terminal Functions

......... 10

4.13

On-Chip SRAM Initialization and Testing

........... 79

2.2

PGE QFP Package Pinout (144-Pin)

............... 10

4.14

External Memory Interface (EMIF)

................. 81

2.3

ZWT BGA Package Ball-Map (337 Ball Grid Array)

4.15

Vectored Interrupt Manager

........................ 88

...................................................... 11

4.16

DMA Controller

..................................... 91

2.4

Terminal Functions

................................. 12

4.17

Real Time Interrupt Module

........................ 93

Device Operating Conditions

....................... 41

4.18

Error Signaling Module

............................. 95

3.1

Absolute Maximum Ratings Over Operating

4.19

Reset / Abort / Error Sources

....................... 99

Free-Air Temperature Range,

...................... 41

4.20

Digital Windowed Watchdog

...................... 101

3.2

Device Recommended Operating Conditions

...... 41

4.21

Debug Subsystem

................................. 102

3.3

Switching Characteristics over Recommended

Peripheral Information and Electrical

Operating Conditions for Clock Domains

........... 42

Specifications

......................................... 113

3.4

Wait States Required

............................... 42

5.1

Peripheral Legend

................................. 113

3.5

Power Consumption Over Recommended

5.2

Multi-Buffered 12bit Analog-to-Digital Converter

Operating Conditions

............................... 43

..................................................... 113

3.6

Input/Output Electrical Characteristics Over

5.3

General-Purpose Input/Output

.................... 122

Recommended Operating Conditions

.............. 44

5.4

Enhanced High-End Timer (N2HET)

.............. 123

3.7

Output Buffer Drive Strengths

...................... 44

5.5

Controller Area Network (DCAN)

.................. 127

3.8

Input Timings

....................................... 45

5.6

Local Interconnect Network Interface (LIN)

....... 128

3.9

Output Timings

..................................... 45

5.7

Serial Communication Interface (SCI)

............ 129

3.10

Low-EMI Output Buffers

............................ 47

5.8

Inter-Integrated Circuit (I2C)

...................... 130

5.9

Multi-Buffered / Standard Serial Peripheral Interface

System Information and Electrical Specifications

..................................................... 133

............................................................. 48

5.10

Ethernet Media Access Controller

................ 145

4.1

Device Power Domains

............................. 48

Mechanical Data

...................................... 148

4.2

Voltage Monitor Characteristics

.................... 49

6.1

Thermal Data

...................................... 148

4.3

Power Sequencing and Power On Reset

.......... 50

6.2

Packaging Information

............................ 148

4.4

Warm Reset (nRST)

................................ 52

4.5

™ CPU Information

............. 53

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