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RM48L540 Datasheet(PDF) 87 Page - Texas Instruments |
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RM48L540 Datasheet(HTML) 87 Page - Texas Instruments |
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87 / 152 page ![]() RM48L940 RM48L740 RM48L540 www.ti.com SPNS175 – SEPTEMBER 2011 Table 4-30. EMIF Synchronous Memory Switching Characteristics (continued) NO. Parameter MIN MAX Unit 8 toh(CLKH-AIV) Output hold time, EMIF_CLK rising to 1 ns EMIFADDR[21:0] and EMIFBA[1:0] invalid 9 td(CLKH-DV) Delay time, EMIF_CLK rising to 7 ns EMIFDATA[15:0] valid 10 toh(CLKH-DIV) Output hold time, EMIF_CLK rising to 1 ns EMIFDATA[15:0] invalid 11 td(CLKH-RASV) Delay time, EMIF_CLK rising to 7 ns EMIFnRAS valid 12 toh(CLKH-RASIV) Output hold time, EMIF_CLK rising to 1 ns EMIFnRAS invalid 13 td(CLKH-CASV) Delay time, EMIF_CLK rising to 7 ns EMIFnCAS valid 14 toh(CLKH-CASIV) Output hold time, EMIF_CLK rising to 1 ns EMIFnCAS invalid 15 td(CLKH-WEV) Delay time, EMIF_CLK rising to 7 ns EMIFnWE valid 16 toh(CLKH-WEIV) Output hold time, EMIF_CLK rising to 1 ns EMIFnWE invalid 17 tdis(CLKH-DHZ) Delay time, EMIF_CLK rising to 7 ns EMIFDATA[15:0] tri-stated 18 tena(CLKH-DLZ) Output hold time, EMIF_CLK rising to 1 ns EMIFDATA[15:0] driving Copyright © 2011, Texas Instruments Incorporated System Information and Electrical Specifications 87 Submit Documentation Feedback focus.ti.com: RM48L940 RM48L740 RM48L540 |
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