LPC178X datasheet(64/120 Pages) NXP

64 / 120 page

LPC178X_7X

All information provided in this document is subject to legal disclaimers.

Preliminary data sheet

Rev. 4 — 1 May 2012

64 of 120

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

The DMA controller can continue to work in Sleep mode and has access to the peripheral

RAMs and all peripheral registers. The flash memory and the main SRAM are not

available in Sleep mode, they are disabled in order to save power.

Wake-up from Sleep mode will occur whenever any enabled interrupt occurs.

7.33.4.2

Deep-sleep mode

In Deep-sleep mode, the oscillator is shut down and the chip receives no internal clocks.

The processor state and registers, peripheral registers, and internal SRAM values are

preserved throughout Deep-sleep mode and the logic levels of chip pins remain static.

The output of the IRC is disabled but the IRC is not powered down to allow fast wake-up.

The RTC oscillator is not stopped because the RTC interrupts may be used as the

wake-up source. The PLL is automatically turned off and disconnected. The clock divider

registers are automatically reset to zero.

The Deep-sleep mode can be terminated and normal operation resumed by either a

Reset or certain specific interrupts that are able to function without clocks. Since all

dynamic operation of the chip is suspended, Deep-sleep mode reduces chip power

consumption to a very low value. Power to the flash memory is left on in Deep-sleep

mode, allowing a very quick wake-up.

Wake-up from Deep-sleep mode can initiated by the NMI, External Interrupts EINT0

through EINT3, GPIO interrupts, the Ethernet Wake-on-LAN interrupt, Brownout Detect,

an RTC Alarm interrupt, a USB input pin transition (USB activity interrupt), a CAN input

pin transition, or a Watchdog Timer time-out, when the related interrupt is enabled.

Wake-up will occur whenever any enabled interrupt occurs.

On wake-up from Deep-sleep mode, the code execution and peripherals activities will

resume after four cycles expire if the IRC was used before entering Deep-sleep mode. If

the main external oscillator was used, the code execution will resume when 4096 cycles

expire. PLL and clock dividers need to be reconfigured accordingly.

7.33.4.3

Power-down mode

Power-down mode does everything that Deep-sleep mode does but also turns off the

power to the IRC oscillator and the flash memory. This saves more power but requires

waiting for resumption of flash operation before execution of code or data access in the

flash memory can be accomplished.

When the chip enters Power-down mode, the IRC, the main oscillator, and all clocks are

stopped. The RTC remains running if it has been enabled and RTC interrupts may be

used to wake up the CPU. The flash is forced into Power-down mode. The PLLs are

automatically turned off and the clock selection multiplexers are set to use the system

clock sysclk (the reset state). The clock divider control registers are automatically reset to

zero. If the Watchdog timer is running, it will continue running in Power-down mode.

On the wake-up of Power-down mode, if the IRC was used before entering Power-down

mode, it will take IRC 60

s to start-up. After this, four IRC cycles will expire before the

code execution can then be resumed if the code was running from SRAM. In the

meantime, the flash wake-up timer then counts 12 MHz IRC clock cycles to make the

100

s flash start-up time. When it times out, access to the flash will be allowed. Users

need to reconfigure the PLL and clock dividers accordingly.

LPC178X Datasheet(PDF) 64 Page - NXP Semiconductors

LPC178X Datasheet(HTML) 64 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL