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LPC178X Datasheet(PDF) 82 Page - NXP Semiconductors |
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LPC178X Datasheet(HTML) 82 Page - NXP Semiconductors |
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82 / 120 page  LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Preliminary data sheet Rev. 4 — 1 May 2012 82 of 120 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 11.2 External memory interface Table 17. Dynamic characteristics: Static external memory interface CL =10 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter[1] Conditions[1] Min Max Unit Read cycle parameters[2] tCSLAV CS LOW to address valid time RD1 1.4 2.5 ns tCSLOEL CS LOW to OE LOW time RD2 [3] 1.3 + Tcy(clk) WAITOEN 2.5 + Tcy(clk) WAITOEN ns tCSLBLSL CS LOW to BLS LOW time RD3; PB = 1 [3] 1.5 3.0 ns tOELOEH OE LOW to OE HIGH time RD4 [3] (WAITRD WAITOEN + 1) T cy(clk) 1.0 (WAITRD WAITOEN + 1) T cy(clk) 1.6 ns tam memory access time RD5 [4] [3] (WAITRD WAITOEN +1) T cy(clk) 7.2 (WAITRD WAITOEN +1) Tcy(clk) 15.5 ns th(D) data input hold time RD6 [5] [3] 0.1 0.1 ns tCSHBLSH CS HIGH to BLS HIGH time PB = 1 1.5 3.0 ns tCSHOEH CS HIGH to OE HIGH time [3] 1.3 2.5 ns tOEHANV OE HIGH to address invalid time [3] 0.09 0.13 ns tdeact deactivation time RD7 [3] 1.4 2.5 ns Write cycle parameters[2] tCSLAV CS LOW to address valid time WR1 1.4 2.5 ns tCSLDV CS LOW to data valid time WR2 1.5 2.9 ns tCSLWEL CS LOW to WE LOW time WR3; PB =1 [3] 1.4 + Tcy(clk) (1 + WAITWEN) 2.5 + Tcy(clk) (1 + WAITWEN) ns tCSLBLSL CS LOW to BLS LOW time WR4; PB = 1 [3] 3.0 3.0 ns tWELWEH WE LOW to WE HIGH time WR5; PB =1 [3] (WAITWR WAITWEN + 1) T cy(clk) 1.0 (WAITWR WAITWEN + 1) T cy(clk) 1.7 ns tBLSLBLSH BLS LOW to BLS HIGH time PB = 1 [3] (WAITWR WAITWEN + 3) T cy(clk) 1.4 (WAITWR WAITWEN + 3) T cy(clk) 2.7 ns tWEHDNV WE HIGH to data invalid time WR6; PB =1 [3] 1.2 + Tcy(clk) 2.1 + Tcy(clk) ns tWEHEOW WE HIGH to end of write time WR7; PB = 1 [6] [3] <tbd> + Tcy(clk) <tbd> + Tcy(clk) ns tBLSHDNV BLS HIGH to data invalid time PB = 1 1.4 2.7 ns tWEHANV WE HIGH to address invalid time PB = 1 [3] 1 + Tcy(clk) 1.7 + Tcy(clk) ns tdeact deactivation time WR8; PB = 0; PB = 1 [3] 1.4 2.5 ns tCSLBLSL CS LOW to BLS LOW WR9; PB = 0 [3] 3.0 + Tcy(clk) (1 + WAITWEN) 3.0 + Tcy(clk) (1 + WAITWEN) ns |
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