LPC178X datasheet(68/120 Pages) NXP

68 / 120 page

LPC178X_7X

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Preliminary data sheet

Rev. 4 — 1 May 2012

68 of 120

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

7.34.4 APB interface

The APB peripherals are split into two separate APB buses in order to distribute the bus

bandwidth and thereby reducing stalls caused by contention between the CPU and the

GPDMA controller.

7.34.5 AHB multilayer matrix

The LPC178x/7x use an AHB multilayer matrix. This matrix connects the instruction

(I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the

main (64 kB) SRAM, and the Boot ROM. The GPDMA can also access all of these

memories. Additionally, the matrix connects the CPU system bus and all of the DMA

controllers to the various peripheral functions.

7.34.6 External interrupt inputs

The LPC178x/7x include up to 30 edge sensitive interrupt inputs combined with one level

sensitive external interrupt input as selectable pin function. The external interrupt input

can optionally be used to wake up the processor from Power-down mode.

7.34.7 Memory mapping control

The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table

to alternate locations in the memory map. This is controlled via the Vector Table Offset

The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address

space. The vector table must be located on a 128 word (512 byte) boundary because the

NVIC on the LPC178x/7x is configured for 128 total interrupts.

7.35 Debug control

Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and

trace functions are supported in addition to a standard JTAG debug and parallel trace

functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four

watch points.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

LPC178X Datasheet(PDF) 68 Page - NXP Semiconductors