S29CD032J datasheet(28/81 Pages) SPANSION

28 / 81 page

S29CD-J and S29CL-J Flash Family

S29CD-J_CL-J_00_B7 October 11, 2012

Da ta

Sh e e t

Figure 8.3 End of Burst Indicator (IND/WAIT#) Timing for Linear 4 Double Word Burst Operation

Note

Operation is shown for the 32-bit data bus. Figure shown with 3-CLK initial access delay configuration, linear address, 4-doubleword burst,

output on rising CLK edge, data hold for 1-CLK, IND/WAIT# asserted on the last transfer before wrap-around.

8.4.2

Initial Burst Access Delay

Initial Burst Access Delay is defined as the number of clock cycles that must elapse from the first valid clock

edge after ADV# assertion (or the rising edge of ADV#) until the first valid CLK edge when the data is valid.

Burst access is initiated and the address is latched on the first rising CLK edge when ADV# is active or upon

a rising ADV# edge, whichever comes first. The Initial Burst Access Delay is determined in the Configuration

Figure 8.4 for the Initial Burst Delay Control timing diagram. Note that the Initial Access Delay for a burst

access has no effect on asynchronous read operations.

Table 8.3 Valid Configuration Register Bit Definition for IND/WAIT#

CR9

(DOC)

CR8

(WC)

CR6

(CC)

Definition

IND/WAIT# = VIL for 1-CLK cycle, Active on last transfer, Driven on rising CLK edge

IND/WAIT# = VIL for 1-CLK cycle, Active on second to last transfer, Driven on rising

CLK edge

CE#

CLK

ADV#

Addresses

OE#

Data

Address 1

Address 2

Invalid

Address 1 Latched

3 Clock Delay

IND/WAIT#

VIL

VIH

Table 8.4 Burst Initial Access Delay

CR13

CR12

CR11

CR10

Initial Burst Access (CLK cycles)

000

001

010

011

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