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S29CD032J Datasheet(PDF) 41 Page - SPANSION |
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S29CD032J Datasheet(HTML) 41 Page - SPANSION |
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41 / 81 page ![]() October 11, 2012 S29CD-J_CL-J_00_B7 S29CD-J and S29CL-J Flash Family 41 Data She e t Figure 8.8 Toggle Bit Algorithm Notes 1. Read toggle bit with two immediately consecutive reads to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. 8.8.5 DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a 1. This is a failure condition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a 1. Under both these conditions, the system issues the reset command to return the device to reading array data. START No Yes Yes DQ5 = 1? No Yes DQ6 = Toggle? No Read Byte (DQ0-DQ7) Address = VA DQ6 = Toggle? Read Byte Twice (DQ0-DQ7) Adrdess = VA Read Byte (DQ0-DQ7) Address = VA FAIL PASS (Note 1) (Notes 1, 2) |
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