S29CD032J datasheet(71/81 Pages) SPANSION

71 / 81 page

October 11, 2012 S29CD-J_CL-J_00_B7

S29CD-J and S29CL-J Flash Family

Data

She e t

18.8

Erase and Programming Performance

Notes

1. Typical program and erase times assume the following conditions: 25°C, 2.5V VCC, 100K cycles. Additionally, programming typicals assume checkerboard

pattern.

2. Under worst case conditions of 145°C, VCC = 2.5V, 1M cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 20.1 and Table 20.2 for further

information on command definitions.

6. PPBs have a program/erase cycle endurance of 100 cycles.

7. Guaranteed cycles per sector is 100K minimum.

18.9

PQFP and Fortified BGA Pin Capacitance

Notes

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0 MHz.

Table 18.7 Erase and Programming Performance

Parameter

Typ

(Note 1)

Max

(Note 2)

Unit

Comments

Sector Erase Time

0.5

Excludes 00h programming prior to erasure

(Note 4)

Chip Erase Time

16 Mb = 23

32 Mb = 46

16 Mb = 230

32 Mb = 460

Double Word Program Time

130

µs

Excludes system level overhead (Note 5)

Accelerated Double Word Program Time

130

µs

Accelerated Chip Program Time

16 Mb = 5

32 Mb = 10

16 Mb = 50

32 Mb = 100

Chip Program Time, x32 (Note 3)

16 Mb = 12

32 Mb = 24

16 Mb = 120

32 Mb = 240

Table 18.8 PQFP and Fortified BGA Pin Capacitance

Parameter Symbol

Parameter Description

Test Setup

Typ

Max

Unit

CIN

Input Capacitance

VIN = 0

7.5

COUT

Output Capacitance

VOUT = 0

8.5

CIN2

Control Pin Capacitance

VIN = 0

7.5

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