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S29CD032J Datasheet(PDF) 80 Page - SPANSION

Part # S29CD032J
Description  32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-Only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O?
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Manufacturer  SPANSION [SPANSION]
Direct Link  http://www.spansion.com
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S29CD032J Datasheet(HTML) 80 Page - SPANSION

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S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
Da ta
Sh e e t
VCC and VIO Power-up And Power-
down Sequencing
Added reference to timing section.
Standby Mode
Changed Vcc ± 0.2V to Vcc ± 10%.
Figure: Test Setup
Removed Note “Diodes are IN3064 or equivalent”.
Table: Alternate CE# Controlled Erase/
Program Operations
Corrected values for tDH with separate values for 16 Mb and 32 Mb.
Table: Memory Array Command
Definitions (x32 Mode)
Cleaned up Notes.
Revision B4 (October 30, 2009)
Absolute Maximum Ratings
Corrected Address, Data, Control Signals identifiers to correctly distinguish different ratings
between CL016L, CL032J, CD016J, and CD032J.
DC Characteristics
Added line item to distinguish VIHCLK value differences between CL-J and CD-J.
Synchronous Operation
Corrected Figure “Burst Mode Read (x32 Mode)” to reflect max linear burst length of 8 double words
instead of 32.
Hardware Reset (RESET#)
Corrected Table “Burst Initial Access Delay”: changed tREADY2, tRP, and tREADY3 set up to Min
instead of Max.
Corrected Figure “RESET# Timings” to add tREADY2 to timing diagram for bank not executing
embedded algorithm.
Revision B5 (May 25, 2011)
Physical Dimensions/Connection
Diagrams
On the 80-ball Fortified BGA Connection Diagram, corrected the K1 pin name from VCCQ to VIO.
Revision B6 (March 15, 2012)
Global
Added LAD080 Fortified BGA package option and drawing.
Additional Resources
Updated relevant application note links.
Revision History
Corrected heading for May 25, 2011 edits from revision B4 to B5.
Revision B7 (October 11, 2012)
Valid Combinations
Updated Valid Combinations table to add clarity and make explicit which offerings require a
customer to “contact factory for availability”.
Asynchronous Operations
In Figure 18.3, “Asynchronous Command Write Timing”, corrected the tWC measurement to be of
the Stable Address period, not the Valid Data period.
Erase/Program Operations
In Table 18.5, “Erase/Program Operations”, corrected JEDEC symbol tAVAV to tAVAX.
In Table 18.5, merged redundant rows tGHWL and tWEH.
In Figures 18.8 “Program Operation Timings” and 18.9 “Chip/Sector Erase Operation Timings”,
corrected tAH measurement to be from the falling edge of WE#.
Section
Description



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