LPC81XM datasheet(27/67 Pages) NXP

27 / 67 page

LPC81xM

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Objective data sheet

Rev. 1.0 — 7 November 2012

27 of 67

NXP Semiconductors

LPC81xM

32-bit ARM Cortex-M0+ microcontroller

1. CRP1 disables access to the chip via the SWD and allows partial flash update

(excluding flash sector 0) using a limited set of the ISP commands. This mode is

useful when CRP is required and flash field updates are needed but all sectors cannot

be erased.

2. CRP2 disables access to the chip via the SWD and only allows full flash erase and

update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected, fully disables any access to the chip

via the SWD pins and the ISP. This mode effectively disables ISP override using

PIO0_1 pin as well. If necessary, the application must provide a flash update

mechanism using IAP calls or using a call to the reinvoke ISP command to enable

flash update via the USART.

In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be

disabled. For details, see the LPC800 user manual.

7.21.4 APB interface

The APB peripherals are located on one APB bus.

7.21.5 AHBLite

The AHBLite connects the CPU bus of the ARM Cortex-M0+ to the flash memory, the

main static RAM, the CRC, and the ROM.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

LPC81XM Datasheet(PDF) 27 Page - NXP Semiconductors