LPC81XM datasheet(39/67 Pages) NXP

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LPC81xM

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Objective data sheet

Rev. 1.0 — 7 November 2012

39 of 67

NXP Semiconductors

LPC81xM

32-bit ARM Cortex-M0+ microcontroller

10.3 Peripheral power consumption

The supply current per peripheral is measured as the difference in supply current between

the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG

and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both

registers and no code is executed. Measured on a typical sample at Tamb =25 C. Unless

noted otherwise, the system oscillator and PLL are running in both measurements.

The supply currents are shown for system clock frequencies of 12 MHz and 30 MHz.

Table 10.

Power consumption for individual analog and digital blocks

Peripheral

Typical supply current in

Notes

n/a

12 MHz

30 MHz

IRC

<tbd>

System oscillator running; PLL off; independent

of main clock frequency.

System oscillator

at 12 MHz

<tbd>

IRC running; PLL off; independent of main clock

frequency.

Watchdog

oscillator at

500 kHz/2

<tbd>

System oscillator running; PLL off; independent

of main clock frequency.

BOD

<tbd>

Independent of main clock frequency.

Main PLL

<tbd>

CLKOUT

<tbd>

Main clock divided by 4 in the CLKOUTDIV

SCT

<tbd>

MRT

<tbd>

WKT

<tbd>

GPIO

<tbd>

GPIO pins configured as outputs and set to

LOW. Direction and pin state are maintained if

the GPIO is disabled in the SYSAHBCLKCFG

interrupt/pattern

match

<tbd>

IOCON

<tbd>

I2C

<tbd>

ROM

<tbd>

SPI0

<tbd>

SPI1

<tbd>

USART0

<tbd>

USART1

<tbd>

USART2

<tbd>

WWDT

<tbd>

Main clock selected as clock source for the

WDT.

Comparator

<tbd>

CRC

<tbd>

SWM

<tbd>

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