LPC81XM datasheet(16/67 Pages) NXP

16 / 67 page

LPC81xM

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Objective data sheet

Rev. 1.0 — 7 November 2012

16 of 67

NXP Semiconductors

LPC81xM

32-bit ARM Cortex-M0+ microcontroller

• An entire port value can be written in one instruction.

• Mask, set, and clear operations are supported for the entire port.

All GPIO port pins are fixed-pin functions that are enabled or disabled on the pins by the

switch matrix. Therefore each GPIO port pin is assigned to one specific pin and cannot be

moved to another pin. Except for pins SWDIO/PIO0_2, SWCLK/PIO0_3, and

RESET/PIO0_5, the switch matrix enables the GPIO port pin function by default.

7.10.1 Features

• Bit level port registers allow a single instruction to set and clear any number of bits in

one write operation.

• Direction control of individual bits.

• All I/O default to inputs with internal pull-up resistors enabled after reset - except for

the I2C-bus true open-drain pins PIO0_2 and PIO0_3.

• Pull-up/pull-down configuration, repeater, and open-drain modes can be programmed

through the IOCON block for each GPIO pin (see Figure 7).

• Control of the digital output slew rate allowing to switch more outputs simultaneously

without degrading the power/ground distribution of the device.

7.11 Pin interrupt/pattern match engine

The pin interrupt block configures up to eight pins from all digital pins for providing eight

external interrupts connected to the NVIC.

The pattern match engine can be used, in conjunction with software, to create complex

state machines based on pin inputs.

Any digital pin, independently of the function selected through the switch matrix, can be

configured through the SYSCON block as input to the pin interrupt or pattern match

engine. The registers that control the pin interrupt or pattern match engine are located on

the IO+ bus for fast single-cycle access.

7.11.1 Features

• Pin interrupts

– Up to eight pins can be selected from all digital pins as edge- or level-sensitive

interrupt requests. Each request creates a separate interrupt in the NVIC.

– Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.

– Level-sensitive interrupt pins can be HIGH- or LOW-active.

– Pin interrupts can wake up the LPC81xM from sleep mode, deep-sleep mode, and

deep power-down mode.

• Pin interrupt pattern match engine

– Up to 8 pins can be selected from all digital pins to contribute to a boolean

expression. The boolean expression consists of specified levels and/or transitions

on various combinations of these pins.

– Each minters (product term) comprising the specified boolean expression can

generate its own, dedicated interrupt request.

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