LPC81XM datasheet(47/67 Pages) NXP

47 / 67 page

LPC81xM

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Objective data sheet

Rev. 1.0 — 7 November 2012

47 of 67

NXP Semiconductors

LPC81xM

32-bit ARM Cortex-M0+ microcontroller

[8]

The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than

the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if

the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the

data must be valid by the set-up time before it releases the clock.

[9]

tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in

transmission and the acknowledge.

[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement

tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the

LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must

output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the

Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must

meet this set-up time.

11.7 SPI interfaces

The maximum data bit rate is 30 Mbit/s in slave and master modes.

Remark: SPI functions can be assigned to all digital pins. The characteristics are valid for

all digital pins except the open-drain pins PIO0_10 and PIO0_11.

Fig 27. I2C-bus pins clock timing

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Table 18.

Dynamic characteristics of SPI pins

Tamb = 40 C to 85 C; CL = <tbd>; 1.8 V <= VDD <= 3.6 V. Simulated parameters; values guaranteed by design.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

SPI master (in SPI mode)

Tcy(clk)

clock cycle time

full-duplex mode

[1]

<tbd>

when only transmitting [1]

<tbd>

tDS

data set-up time

in SPI mode

2.4 V

 V

DD  3.6 V

<tbd>

2.0 V

 V

DD < 2.4 V

<tbd>

1.8 V

 V

DD < 2.0 V

<tbd>

tDH

data hold time

in SPI mode

<tbd>

tv(Q)

data output valid time in SPI mode

<tbd>

th(Q)

data output hold time in SPI mode

<tbd>

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