 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
WM8310 Datasheet(PDF) 131 Page - Wolfson Microelectronics plc |
|
|
|||||||||||||||||||||||||||||
WM8310 Datasheet(HTML) 131 Page - Wolfson Microelectronics plc |
|
|
131 / 291 page  Pre-Production WM8310 w PP, May 2012, Rev 3.1 131 GPn_FN GPIO INPUT FUNCTION DESCRIPTION DE-BOUNCE TIME Ah Hardware Enable 1 Control input for enabling one or more DC-DC Converters and LDO Regulators. See Section 15. 32 s to 64s Bh Hardware Enable 2 Control input for enabling one or more DC-DC Converters and LDO Regulators. See Section 15. 32 s to 64s Ch Hardware Control input 1 Control input for selecting the operating mode and/or output voltage of one or more DC-DC Converters and LDO Regulators. See Section 15. 32 s to 64s Dh Hardware Control input 2 Control input for selecting the operating mode and/or output voltage of one or more DC-DC Converters and LDO Regulators. See Section 15. 32 s to 64s Eh Hardware Control input 1 Control input for selecting the operating mode and/or output voltage of one or more DC-DC Converters and LDO Regulators. See Section 15. 32ms to 64ms Fh Hardware Control input 2 Control input for selecting the operating mode and/or output voltage of one or more DC-DC Converters and LDO Regulators. See Section 15. 32ms to 64ms Table 72 List of GPIO Input Functions Further details of the GPIO input de-bounce time are noted in Section 21.3. GPn_FN GPIO OUTPUT FUNCTION DESCRIPTION 0h GPIO GPIO output. Logic level is set by writing to the GPn_LVL register bits. See Section 21.3. 1h Oscillator clock 32.768kHz clock output. See Section 13. 2h ON state Logic output indicating that the WM8310 is in the ON state. See Section 11.5. 3h SLEEP state Logic output indicating that the WM8310 is in the SLEEP state. See Section 11.5. 4h Power State Change Logic output asserted whenever a Power On Reset, or an ON, OFF, SLEEP or WAKE transition has completed. Under default polarity (GPn_POL=1), the logic level is the same as the PS_INT interrupt status flag. Note that, if any of the associated Secondary interrupts is masked, then the respective event will not affect the Power State Change GPIO output. See Section 11.2 and Section 11.4. 8h DC-DC1 DVS Done Logic output indicating that DC-DC1 buck converter DVS slew has been completed. This signal is temporarily de-asserted during voltage transitions (including non-DVS transitions). See Section 15.6. 9h DC-DC2 DVS Done Logic output indicating that DC-DC1 buck converter DVS slew has been completed. This signal is temporarily de-asserted during voltage transitions (including non-DVS transitions). See Section 15.6. Ah External Power Enable 1 Logic output assigned to one of the timeslots in the ON/OFF and SLEEP/WAKE sequences. This can be used for sequenced control of external circuits. See Section 15.3. Bh External Power Enable 2 Logic output assigned to one of the timeslots in the ON/OFF and SLEEP/WAKE sequences. This can be used for sequenced control of external circuits. See Section 15.3. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
