WM8310 datasheet(132/291 Pages) WOLFSON

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WM8310

Pre-Production

PP, May 2012, Rev 3.1

132

GPn_FN

GPIO OUTPUT

FUNCTION

DESCRIPTION

System Supply

Good (SYSVDD

Good)

Logic output from SYSVDD monitoring circuit. This function

represents the internal SYSOK signal. See Section 24.4.

Converter Power

Good

(PWR_GOOD)

Status output indicating that all selected DC-DC Converters and

LDO Regulators are operating correctly. Only asserted in ON

and SLEEP modes. See Section 15.14.

External Power

Clock

2MHz clock output suitable for clocking external DC-DC

Converters. This clock signal is synchronized with the WM8310

DC-DC Converters clocking signal. See Section 13.

This clock output is only enabled when either of the External

Power Enable signals (EPE1 or EPE2) is asserted. These

signals can be assigned to one of the timeslots in the ON/OFF

and SLEEP/WAKE sequences. See Section 15.3.

Auxiliary Reset

Logic output indicating a Reset condition. This signal is

asserted in the OFF state. The status in SLEEP mode is

configurable. See Section 11.7.

Note that the default polarity for this function (GPn_POL=1) is

“Active High”. Setting GPn_POL=0 will select “Active Low”

function.

Table 73 List of GPIO Output Functions

21.3 CONFIGURING GPIO PINS

The GPIO pins are configured using the Resister fields defined in Table 74.

The function of each GPIO is selected using the GPn_FN register field. The pin direction field

GPn_DIR selects between input functions and output functions. See Section 21.2 for a summary of

the available GPIO functions.

The polarity of each GPIO can be configured using the GPn_POL bits. This inversion is effective both

on GPIO inputs and outputs. When GPn_POL = 1, the non-inverted ‘Active High’ polarity applies. The

opposite logic can be selected by setting GPn_POL = 0.

The voltage power domain of each GPIO is determined by the GPn_PWR_DOM register. Note that

the available options vary between different GPIO pins, as described in Table 76.

A GPIO output may be either CMOS driven or Open Drain. This is selected using the GPn_OD bits.

Internal pull-up or pull-down resistors can be enabled on each pin using the GPn_PULL field. Both

resistors are available for use when the associated GPIO is an input. When the GPIO pin is

configured as an Open Drain output, the internal pull-up resistor may be required if no external pull-up

resistors are present.

The GPIO pins may be enabled or tri-stated using the GPn_ENA register field. When GPn_ENA = 0,

the respective pin is tri-stated. A tri-stated pin exhibits high impedance to any external circuit and is

disconnected from the internal GPIO circuits. The pull-up and pull-down resistors are disabled when a

GPIO pin is tri-stated.

GPIO pins can generate an interrupt (see Section 21.4). The GPn_INT_MODE field selects whether

the interrupt occurs on a single edge only, or else on both rising and falling edges. When single edge

is selected, the active edge is the rising edge (when GPn_POL = 1) or the falling edge (when

GPn_POL = 0.

WM8310 Datasheet(PDF) 132 Page - Wolfson Microelectronics plc

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