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WM8310 Datasheet(PDF) 180 Page - Wolfson Microelectronics plc |
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WM8310 Datasheet(HTML) 180 Page - Wolfson Microelectronics plc |
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180 / 291 page  WM8310 Pre-Production w PP, May 2012, Rev 3.1 180 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 7 PPM_INT 0 Power Path Management primary interrupt 0 = No interrupt 1 = Interrupt is asserted 6 CS_INT 0 Current Sink primary interrupt 0 = No interrupt 1 = Interrupt is asserted 5 RTC_INT 0 Real Time Clock primary interrupt 0 = No interrupt 1 = Interrupt is asserted 4 OTP_INT 0 OTP Memory primary interrupt 0 = No interrupt 1 = Interrupt is asserted 2 CHG_INT 0 Battery Charger primary interrupt 0 = No interrupt 1 = Interrupt is asserted 1 HC_INT 0 High Current primary interrupt 0 = No interrupt 1 = Interrupt is asserted 0 UV_INT 0 Undervoltage primary interrupt 0 = No interrupt 1 = Interrupt is asserted Register 4010h System Interrupts REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R16401 (4011h) Interrupt Status 1 15 PPM_SYSLO_ EINT 0 Power Path SYSLO interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 14 PPM_PWR_SR C_EINT 0 Power Path Source interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 13 PPM_USB_CU RR_EINT 0 Power Path USB Current interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 12 ON_PIN_CINT 0 ON pin interrupt. (Rising and Falling Edge triggered) Note: Cleared when a ‘1’ is written. 11 WDOG_TO_EI NT 0 Watchdog timeout interrupt. (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 8 AUXADC_DAT A_EINT 0 AUXADC Data Ready interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 7 AUXADC_DCO MP4_EINT 0 AUXADC Digital Comparator 4 interrupt (Trigger is controlled by DCMP4_GT) Note: Cleared when a ‘1’ is written. 6 AUXADC_DCO MP3_EINT 0 AUXADC Digital Comparator 3 interrupt (Trigger is controlled by DCMP3_GT) Note: Cleared when a ‘1’ is written. |
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