WM8310 datasheet(255/291 Pages) WOLFSON

255 / 291 page

Pre-Production

WM8310

PP, May 2012, Rev 3.1

255

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

FLL_AUTO

FLL Automatic Mode Enable

0 = Manual configuration mode

1 = Automatic configuration mode

(To enable the FLL output, FLL_ENA must also be set

in Automatic mode)

2:0

FLL_AUTO_FR

EQ [2:0]

000

FLL Automatic Mode Frequency select

000 = 2.048MHz

001 = 11.2896MHz

010 = 12MHz

011 = 12.288MHz

100 = 19.2MHz

101 = 22.5792MHz

110 = 24MHz

111 = 24.576MHz

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R16530

(4092h) FLL

Control 1

FLL_FRAC

Fractional enable

0 = Integer Mode

1 = Fractional Mode

Integer mode offers reduced power consumption.

Fractional mode offers best FLL performance, provided

also that N.K is a non-integer value.

FLL_ENA

FLL Enable

0 = Disabled

1 = Enabled

Note - this bit is reset to 0 when the OFF power state is

entered.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R16531

(4093h) FLL

Control 2

13:8

FLL_OUTDIV

[5:0]

00_0000

FOUT clock divider

000000 = Reserved

000001 = Reserved

000010 = Reserved

000011 = 4

000100 = 5

000101 = 6

…

111110 = 63

111111 = 64

(FOUT = FVCO / FLL_OUTDIV)

6:4

FLL_CTRL_RA

TE [2:0]

000

Frequency of the FLL control block

000 = FVCO / 1 (Recommended value)

001 = FVCO / 2

010 = FVCO / 3

011 = FVCO / 4

100 = FVCO / 5

101 = FVCO / 6

WM8310 Datasheet(PDF) 255 Page - Wolfson Microelectronics plc

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