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WM8310 Datasheet(PDF) 256 Page - Wolfson Microelectronics plc |
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WM8310 Datasheet(HTML) 256 Page - Wolfson Microelectronics plc |
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256 / 291 page ![]() WM8310 Pre-Production w PP, May 2012, Rev 3.1 256 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 110 = FVCO / 7 111 = FVCO / 8 Recommended that this register is not changed from default. 2:0 FLL_FRATIO [2:0] 000 FVCO clock divider 000 = 1 001 = 2 010 = 4 011 = 8 1XX = 16 000 recommended for high FREF 011 recommended for low FREF Register 4093h FLL Control 2 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R16532 (4094h) FLL Control 3 15:0 FLL_K [15:0] 0000_0000 _0000_000 0 Fractional multiply for FREF (MSB = 0.5) Register 4094h FLL Control 3 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R16533 (4095h) FLL Control 4 14:5 FLL_N [9:0] 01_0111_0 111 Integer multiply for FREF (LSB = 1) 3:0 FLL_GAIN [3:0] 0000 Gain applied to error 0000 = x 1 (Recommended value) 0001 = x 2 0010 = x 4 0011 = x 8 0100 = x 16 0101 = x 32 0110 = x 64 0111 = x 128 1XXX = x 256 Recommended that this register is not changed from default. Register 4095h FLL Control 4 |
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