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WM8351 Datasheet(PDF) 177 Page - Wolfson Microelectronics plc |
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WM8351 Datasheet(HTML) 177 Page - Wolfson Microelectronics plc |
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177 / 330 page  Production Data WM8351 w PD, April 2012, Rev 4.5 177 19.7 AUXADC INTERRUPTS The AUXADC has five second-level interrupts which can trigger a first-level System Interrupt, AUXADC_INT (see Section 24). These are described in Table 120. Each AUXADC interrupt in Register R26 can be masked by setting the associated mask bit in Register R34. The AUX_DATARDY_EINT interrupt indicates that new AUXADC data is ready. This bit is cleared when Register R26 is read. Note that this bit is not cleared by reading the measured AUXADC data in Registers R152 to R159. The AUXADC_DCOMPn_EINT interrupts indicate that the selected AUXADC channel on Comparator ‘n’ is beyond the programmed threshold. The DCMPn_GT register bits defined in Table 119 select whether an interrupt indicates the measured value is above the threshold or indicates the measured value is below the threshold. ADDRESS BIT LABEL DESCRIPTION R26 (1Ah) Interrupt Status 2 8 AUXADC_DATARDY_EINT Auxiliary data ready. (Rising Edge triggered) Note: This bit is cleared once read. 7 AUXADC_DCOMP4_EINT DCOMP4 interrupt. (Rising Edge triggered) Note: This bit is cleared once read. 6 AUXADC_DCOMP3_EINT DCOMP3 interrupt. (Rising Edge triggered) Note: This bit is cleared once read. 5 AUXADC_DCOMP2_EINT DCOMP2 interrupt. (Rising Edge triggered) Note: This bit is cleared once read. 4 AUXADC_DCOMP1_EINT DCOMP1 interrupt. (Rising Edge triggered) Note: This bit is cleared once read. R34 (22h) Interrupt Status 2 Mask 8:4 “IM_” + name of respective bit in R26 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Table 120 AUXADC Interrupts |
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