WM8352 datasheet(47/336 Pages) WOLFSON

47 / 336 page

Production Data

WM8352

PD, February 2011, Rev 4.4

The oscillator is enabled by the OSC32K_ENA field, as described in Table 7. It is enabled by default

and remains enabled when the WM8352 is in the OFF or BACKUP state.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R12 (0Ch)

Power

Mgmt (5)

OSC32K_ENA

32kHz crystal oscillator control

0 = 32kHz OSC is disabled

1 = 32kHz OSC is enabled

R218 (DAh)

RTC Tick

Control

Note: OSC32K_ENA can be accessed through R12 or through R218. Reading from or writing to

either register location has the same effect.

Table 7 Enabling the 32kHz Oscillator

If a suitable 32.768kHz clock is already present elsewhere in the system, then it is possible for the

WM8352 to use this clock instead. An external clock can be provided to the WM8352 on pin X1 (with

pin X2 left floating) or else on a GPIO pin configured as a 32kHz input (see Section 20).

In addition to driving the RTC, the 32kHz oscillator signal can be output to a GPIO pin configured as

a 32kHz output; this is possible on GPIO pins 2, 3, 5 and 12 (see Section 20.2).

12.3 CLOCKING AND SAMPLE RATES

Clocks for the ADCs, DACs, DSP core functions, and the digital audio interface are all derived from a

common internal clock source, SYSCLK.

SYSCLK can either be derived directly from MCLK (with a selectable divide by two option, controlled

by MCLK_DIV), or may be generated by the FLL using MCLK or alternate sources as an external

reference. The SYSCLK source is selected by MCLK_SEL. Many commonly-used audio sample

rates can be derived directly from typical MCLK frequencies.

The ADC and DAC sample rates are independently selectable, relative to SYSCLK, using

ADC_CLKDIV and DAC_CLKDIV. These fields must be set according to the required sampling

frequency and depending upon the selected clocking mode. Two clocking modes are provided as

follows. Normal mode allows selection of the commonly used sample rates from typical audio

system clocking frequencies (eg. 12.288MHz); USB mode allows many of these sample rates to be

generated from a 12MHz USB clock. Depending on the available clock sources, USB mode may be

used to save power by supporting 44.1kHz operation.

In Normal mode,



ADC_SYSCLK = 256 x ADC Sampling Frequency



DAC_SYSCLK = 256 x DAC Sampling Frequency

In USB mode,



ADC_SYSCLK = 272 x ADC Sampling Frequency



DAC_SYSCLK = 272 x DAC Sampling Frequency

The above equations determine the required values for ADC_CLKDIV and DAC_CLKDIV. The

clocking mode is selected via the AIF_LRCLKRATE field.

In master mode, BCLK is also derived from SYSCLK via a programmable division set by BCLK_DIV.

In the case where the ADCs and DACs are operating at different sample rates, BCLK must be set

according to whichever is the faster rate. In Master Mode, internal clock divide and phase control

mechanisms ensure that the BCLK, ADCLRCLK and DACLRCLK edges will occur in a predictable

and repeatable position relative to each other and to the data for a given combination of ADC/DAC

sample rates and BCLK settings. In Slave Mode, the host processor must ensure that BCLK,

ADCLRCLK and DACLRCLK are fully synchronised; if these inputs are not synchronised,

unpredictable pops and noise may result.

WM8352 Datasheet(PDF) 47 Page - Wolfson Microelectronics plc

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