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WM8352 Datasheet(PDF) 33 Page - Wolfson Microelectronics plc |
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WM8352 Datasheet(HTML) 33 Page - Wolfson Microelectronics plc |
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33 / 336 page  Production Data WM8352 w PD, February 2011, Rev 4.4 33 10.3 AUDIO INTERFACE TIMING - SLAVE MODE Figure 16 Digital Audio Data Timing – Slave Mode Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, DGND = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns LRCLK set-up time to BCLK rising edge tLRSU 10 ns LRCLK hold time from BCLK rising edge tLRH 10 ns DACDAT hold time from BCLK rising edge tDH 10 ns DACDAT set-up time to BCLK rising edge tDS 10 ns ADCDAT propagation delay from BCLK falling edge tDD 10 ns |
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