WM8352 datasheet(50/336 Pages) WOLFSON

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WM8352

Production Data

PD, February 2011, Rev 4.4

12.3.2

ADC / DAC SAMPLE RATES

The ADC and DAC sample rates are independently selectable, relative to SYSCLK, by setting the

frequency, and according to the selected mode of operation (Normal or USB). The applicable fields

are described in Table 9.

Selection of USB mode enables a 12MHz USB clock to be used to generate the required internal

clock signals. Table 10 describes the available sample rates using four different common MCLK

frequencies. The AIF_LRCLKRATE field must be set as described in Table 9.

In Normal mode, the programmable division set by ADC_CLKDIV must ensure that ADC_SYSCLK is

256 * ADC Sampling Frequency. DAC_CLKDIV must ensure that DAC_SYSCLK is 256 * DAC

Sampling Frequency.

In USB mode, ADC_CLKDIV must ensure that ADC_SYSCLK is 272 * ADC Sampling Frequency.

DAC_CLKDIV must ensure that DAC_SYSCLK is 272 * DAC Sampling Frequency.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R48 (30h)

DAC

Control

AIF_LRCLKRATE

Mode Select

1 = USB mode (272 * Fs)

0 = Normal mode (256 * Fs)

R68 (44h)

ADC Clock

Control

2:0

ADC_CLKDIV [2:0]

000

ADC Sample rate divider

000 = SYSCLK / 1.0

001 = SYSCLK / 1.5

010 = SYSCLK / 2

011 = SYSCLK / 3

100 = SYSCLK / 4

101 = SYSCLK / 5.5

110 = SYSCLK / 6

111 = Reserved

R54 (36h)

DAC Clock

Control

2:0

DAC_CLKDIV [2:0]

000

DAC Sample rate divider

000 = SYSCLK / 1.0

001 = SYSCLK / 1.5

010 = SYSCLK / 2

011 = SYSCLK / 3

100 = SYSCLK / 4

101 = SYSCLK / 5.5

110 = SYSCLK / 6

111 = Reserved

Table 9 ADC / DAC Sample Rate Control

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