WM8352 datasheet(53/336 Pages) WOLFSON

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Production Data

WM8352

PD, February 2011, Rev 4.4

Table 12 shows the maximum word lengths supported for a given SYSCLK and BCLK_DIV,

assuming that one or both the ADCs and DACs are running at maximum rate.

SYSCLK

BCLK DIVIDER

BCLK_DIV

BCLK RATE (MASTER

MODE) (MHZ)

MAXIMUM WORD

LENGTH

12.288 MHz

0000 = SYSCLK / 1

12.288

0001 = SYSCLK / 1.5

8.192

0010 = SYSCLK / 2

6.144

0011 = SYSCLK / 3

4.096

0100 = SYSCLK / 4

3.072

0101 = SYSCLK / 5.5

2.2341818

0110 = SYSCLK / 6

2.048

0111 = SYSCLK / 8

1.536

1000 = SYSCLK / 11

1.117091

1001 = SYSCLK / 12

1.024

1010 = SYSCLK / 16

0.768

1011 = SYSCLK / 22

0.558545

N/A

1100 = SYSCLK / 24

0.512

N/A

1101 = SYSCLK / 32

0.384

N/A

1110 = SYSCLK / 32

0.384

N/A

1111 = SYSCLK / 32

0.384

N/A

11.2896 MHz

0000 = SYSCLK / 1

11.2896

0001 = SYSCLK / 1.5

7.5264

0010 = SYSCLK / 2

5.6448

0011 = SYSCLK / 3

3.7632

0100 = SYSCLK / 4

2.8224

0101 = SYSCLK / 5.5

2.052655

0110 = SYSCLK / 6

1.8816

0111 = SYSCLK / 8

1.4112

1000 = SYSCLK / 11

1.026327

1001 = SYSCLK / 12

0.9408

1010 = SYSCLK / 16

0.7056

1011 = SYSCLK / 22

0.513164

N/A

1100 = SYSCLK / 24

0.4704

N/A

1101 = SYSCLK / 32

0.3528

N/A

1110 = SYSCLK / 32

0.3528

N/A

1111 = SYSCLK / 32

0.3528

N/A

Table 12 BCLK Divider in Master Mode

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