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WM8352 Datasheet(PDF) 51 Page - Wolfson Microelectronics plc |
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WM8352 Datasheet(HTML) 51 Page - Wolfson Microelectronics plc |
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51 / 336 page ![]() Production Data WM8352 w PD, February 2011, Rev 4.4 51 SYSCLK ADC / DAC SAMPLE RATE DIVIDER CLOCKING MODE ADC / DAC SAMPLE RATE 12.2880 MHz 000 = SYSCLK / 1 Normal (256 * Fs) 48 kHz 001 = SYSCLK / 1.5 32 kHz 010 = SYSCLK / 2 24 kHz 011 = SYSCLK / 3 16 kHz 100 = SYSCLK / 4 12 kHz 101 = SYSCLK / 5.5 Not used 110 = SYSCLK / 6 8 kHz 111 = Reserved Reserved 11.2896 MHz 000 = SYSCLK / 1 Normal (256 * Fs) 44.1 kHz 001 = SYSCLK / 1.5 Not used 010 = SYSCLK / 2 22.05 kHz 011 = SYSCLK / 3 Not used 100 = SYSCLK / 4 11.025 kHz 101 = SYSCLK / 5.5 8.018 kHz 110 = SYSCLK / 6 Not used 111 = Reserved Reserved 12.0000 MHz 000 = SYSCLK / 1 USB (272 * Fs) 44.118 kHz 001 = SYSCLK / 1.5 Not used 010 = SYSCLK / 2 22.059 kHz 011 = SYSCLK / 3 Not used 100 = SYSCLK / 4 11.029 kHz 101 = SYSCLK / 5.5 8.021 kHz 110 = SYSCLK / 6 Not used 111 = Reserved Reserved 2.0480 MHz 000 = SYSCLK / 1 Normal (256 * Fs) 8 kHz 001 = SYSCLK / 1.5 Not used 010 = SYSCLK / 2 Not used 011 = SYSCLK / 3 Not used 100 = SYSCLK / 4 Not used 101 = SYSCLK / 5.5 Not used 110 = SYSCLK / 6 Not used 111 = Reserved Reserved Table 10 Derivation of Sample Rates in Normal / USB Modes Note that, in USB mode, the ADC / DAC sample rates do not match exactly with the commonly used sample rates (eg. 44.118 kHz instead of 44.100 kHz). At most, the difference is less than 0.5%, which is within normal accepted tolerances. Data recorded at 44.100 kHz sample rate and replayed at 44.118 kHz will experience a slight (sub 0.5%) pitch shift as a result of this difference. Note: USB mode cannot be used to generate a 48kHz samples rate from a 12MHz MCLK; the FLL should be used in this case. The user must ensure correct synchronisation of data across the digital interfaces. This is particularly important when different sample rates are used, as described above. |
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