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WM8352 Datasheet(PDF) 54 Page - Wolfson Microelectronics plc |
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WM8352 Datasheet(HTML) 54 Page - Wolfson Microelectronics plc |
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54 / 336 page  WM8352 Production Data w PD, February 2011, Rev 4.4 54 12.3.4 ADCLRCLK / DACLRCLK CONTROL In Master Mode, ADCLRCLK and DACLRCLK are derived from BCLK via programmable dividers set by ADCLRC_RATE and DACLRC_RATE. The BCLK frequency is derived from SYSCLK according to BCLK_DIV, as described earlier in Table 11. In Slave Mode, ADCLRCLK and DACLRCLK are generated externally and are input to the CODEC. By default, the LRCLK pin provides the L/R Clock signal for the ADC and the DAC. If a separate L/R Clock is required for the ADC and the DAC, then a GPIO pin must be configured as ADCLRCLK (or ADCLRCB) as described in Section 20. The LRCLK pin can be driven by either ADCLRCLK or by DACLRCLK in Master Mode; this is selected by the LRC_ADC_SEL bit as described in Table 13. Master/Slave operation for ADCLRCLK is controlled by the ADCLRC_ENA register field. Master/Slave operation for DACLRCLK is controlled by the DACLRC_ENA register field. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R70 (46h) ADC LRC Rate 11 ADCLRC_ENA 0 Enables the LRC generation for the ADC 0 = disabled 1 = enabled 10:0 ADCLRC_RATE [10:0] 040h (64 BCLK / LRC) Determines the number of bit clocks per LRC phase (when enabled) 00000000000 = invalid ... 00000000111 = invalid 00000001000 = 8 BCPS … 11111111111 = 2047 BCPS R53 (35h) DAC LRC Rate 11 DACLRC_ENA 0 Enables DAC LRC generation in Master mode 0 = disabled 1 = enabled 10:0 DACLRC_RATE [10:0] 040h (64 BCLK / LRC) Determines the number of bit clocks per LRC phase (when enabled) 00000000000 = invalid ... 00000000111 = invalid 00000001000 = 8 BCPS … 11111111111 = 2047 BCPS R41 (29h) Clock Control 2 15 LRC_ADC_SEL 0 Selects either ADCLRCLK or DACLRCLK to drive LRCLK pin in Master Mode 0 = DACLRCLK 1 = ADCLRCLK Table 13 ADCLRCLK / DACLRCLK Control |
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