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WM8352 Datasheet(PDF) 315 Page - Wolfson Microelectronics plc |
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WM8352 Datasheet(HTML) 315 Page - Wolfson Microelectronics plc |
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315 / 336 page ![]() Production Data WM8352 w PD, February 2011, Rev 4.4 315 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R225 (E1h) DCDC/LDO status 15 LS_STS 0 Readback of the raw signal value. Allow direct control of this signal's input to the debounce logic when the ANALOG_OVRDE bit is set to 1. Reset by state machine. 11 LDO4_STS 0 Readback of the raw signal value. Allow direct control of this signal's input to the debounce logic when the ANALOG_OVRDE bit is set to 1. Reset by state machine. 10 LDO3_STS 0 Readback of the raw signal value. Allow direct control of this signal's input to the debounce logic when the ANALOG_OVRDE bit is set to 1. Reset by state machine. 9 LDO2_STS 0 Readback of the raw signal value. Allow direct control of this signal's input to the debounce logic when the ANALOG_OVRDE bit is set to 1. Reset by state machine. 8 LDO1_STS 0 Readback of the raw signal value. Allow direct control of this signal's input to the debounce logic when the ANALOG_OVRDE bit is set to 1. Reset by state machine. 5 DC6_STS 0 Readback of the raw signal value. Allow direct control of this signal's input to the debounce logic when the ANALOG_OVRDE bit is set to 1. Reset by state machine. 4 DC5_STS 0 Readback of the raw signal value. Allow direct control of this signal's input to the debounce logic when the ANALOG_OVRDE bit is set to 1. Reset by state machine. 3 DC4_STS 0 Readback of the raw signal value. Allow direct control of this signal's input to the debounce logic when the ANALOG_OVRDE bit is set to 1. Reset by state machine. 2 DC3_STS 0 Readback of the raw signal value. Allow direct control of this signal's input to the debounce logic when the ANALOG_OVRDE bit is set to 1. Reset by state machine. 1 DC2_STS 0 Readback of the raw signal value. Allow direct control of this signal's input to the debounce logic when the ANALOG_OVRDE bit is set to 1. Reset by state machine. 0 DC1_STS 0 Readback of the raw signal value. Allow direct control of this signal's input to the debounce logic when the ANALOG_OVRDE bit is set to 1. Reset by state machine. Register E1h DCDC/LDO status |
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