CY8C54LP datasheet(64/117 Pages) CYPRESS

64 / 117 page

PRELIMINARY

PSoC® 5LP: CY8C54LP Family

Datasheet

Document Number: 001-84934 Rev. **

Page 64 of 117

IDD[15]

Sleep Mode[16]

CPU = OFF

RTC = ON (= ECO32K ON, in

low-power mode)

Sleep timer = ON (= ILO ON at

1kHz)[17]

WDT = OFF

I2C Wake = OFF

Comparator = OFF

POR = ON

Boost = OFF

SIO pins in single ended input,

unregulated output mode

VDD = VDDIO = 4.5–5.5 V

T = –40 °C

–

1.9

3.1

µA

T = 25 °C

–

2.4

3.6

T = 85 °C

–

VDD = VDDIO = 2.7–3.6 V

T = –40 °C

–

1.7

3.1

T = 25 °C

–

3.6

T = 85 °C

–

4.2

VDD = VDDIO = 1.71–1.95 V T = –40 °C

–

1.6

3.1

T = 25 °C

–

1.9

3.6

T = 85 °C

–

4.2

Comparator = ON

CPU = OFF

RTC = OFF

Sleep timer = OFF

WDT = OFF

I2C Wake = OFF

POR = ON

Boost = OFF

SIO pins in single ended input,

unregulated output mode

VDD = VDDIO = 2.7–3.6V

T = 25 °C

–

4.2

µA

I2C Wake = ON

CPU = OFF

RTC = OFF

Sleep timer = OFF

WDT = OFF

Comparator = OFF

POR = ON

Boost = OFF

SIO pins in single ended input,

unregulated output mode

VDD = VDDIO = 2.7–3.6V

T = 25 °C

–

1.7

3.6

µA

Hibernate Mode[18]

Hibernate mode current

All regulators and oscillators off.

SRAM retention

GPIO interrupts are active

Boost = OFF

SIO pins in single ended input,

unregulated output mode

VDD = VDDIO = 4.5–5.5 V T = –40 °C

–

0.2

µA

T = 25 °C

–

0.24

T = 85 °C

–

2.6

VDD = VDDIO = 2.7–3.6 V T = –40 °C

–

0.11

T = 25 °C

–

0.3

T = 85 °C

–

VDD = VDDIO = 1.71–1.95 V T = –40 °C

–

0.9

T = 25 °C

–

0.11

T = 85 °C

–

1.8

IDDAR

Analog current consumption while

device is reset[19]

VDDA ≤ 3.6 V

–

0.3

0.6

VDDA > 3.6 V

–

1.4

3.3

IDDDR

Digital current consumption while

device is reset[19]

VDDD ≤ 3.6 V

–

1.1

3.1

VDDD > 3.6 V

–

0.7

3.1

IDD_PROG Current consumption while device

programming. Sum of digital,

analog, and I/Os: IDDD + IDDA +

IDDIOX

–15

Table 11-2. DC Specifications

(continued)

Parameter

Description

Conditions

Min

Typ

Max

Units

Notes

16. If VCCD and VCCA are externally regulated, the voltage difference between VCCD and VCCA must be less than 50 mV.

17. Sleep timer generates periodic interrupts to wake up the CPU. This specification applies only to those times that the CPU is off.

18. If VCCD and VCCA are externally regulated, the voltage difference between VCCD and VCCA must be less than 50 mV.

19. Based on device characterization (Not production tested). USBIO pins tied to ground (VSSD).

20. Based on device characterization (not production tested).

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