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CY8C54LP Datasheet(PDF) 11 Page - Cypress Semiconductor |
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CY8C54LP Datasheet(HTML) 11 Page - Cypress Semiconductor |
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11 / 117 page ![]() PRELIMINARY PSoC® 5LP: CY8C54LP Family Datasheet Document Number: 001-84934 Rev. ** Page 11 of 117 Figure 4-1. ARM Cortex-M3 Block Diagram Nested Vectored Interrupt Controller (NVIC) Debug Block (Serial and JTAG) Embedded Trace Module (ETM) Trace Port Interface Unit (TPIU) Interrupt Inputs JTAG/SWD Trace Pins: 5 for TRACEPORT or 1 for SWV mode Cortex M3 CPU Core I- Bus S-Bus D-Bus 256 KB ECC Flash Cache 32 KB SRAM DMA AHB Bridge & Bus Matrix PHUB GPIO & EMIF Prog. Digital Prog. Analog Special Functions Peripherals AHB Spokes AHB AHB AHB Bus Matrix Cortex M3 Wrapper C-Bus Data Watchpoint and Trace (DWT) Instrumentation Trace Module (ITM) Flash Patch and Breakpoint (FPB) Bus Matrix 32 KB SRAM Bus Matrix |
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