CY8C54LP datasheet(82/117 Pages) CYPRESS

82 / 117 page

PRELIMINARY

PSoC® 5LP: CY8C54LP Family

Datasheet

Document Number: 001-84934 Rev. **

Page 82 of 117

Figure 11-32. SAR ADC Noise Histogram, 1000 samples,

700 ksps, Internal Reference No Bypass, VIN = VREF/2

Figure 11-34. SAR ADC Noise Histogram, 1000

samples, 700 ksps, Internal Reference Bypassed,

VIN = VREF/2

Figure 11-33. SR ADC Noise Histogram, 1000 samples,

700 ksps, External Reference, VIN = VREF/2

Notes

38. Based on device characterization (Not production tested).

39. The resistance of the analog global and analog mux bus is high if VDDA ≤ 2.7 V, and the chip is in either sleep or hibernate mode. Use of analog global and analog

mux bus under these conditions is not recommended.

Table 11-22. SAR ADC AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Fclk

SAR clock frequency

–

MHz

Conversion time

One conversion requires 18 SAR

clocks. Maximum sample rate is 1

Msps

–

µs

Startup time[38]

–

µs

SINAD

Signal-to-noise ratio[38]

–

THD

Total harmonic distortion[38]

–

0.02

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