CY8C54LP datasheet(25/117 Pages) CYPRESS

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PRELIMINARY

PSoC® 5LP: CY8C54LP Family

Datasheet

Document Number: 001-84934 Rev. **

Page 25 of 117

6.2 Power System

The power system consists of separate analog, digital, and I/O supply pins, labeled VDDA, VDDD, and VDDIOX, respectively. It also

includes two internal 1.8 V regulators that provide the digital (VCCD) and analog (VCCA) supplies for the internal core logic. The output

pins of the regulators (VCCD and VCCA) and the VDDIO pins must have capacitors connected as shown in Figure 6-4. The two VCCD

pins must be shorted together, with as short a trace as possible, and connected to a 1 µF ±10% X5R capacitor. The power system

also contains a sleep regulator, an I2C regulator, and a hibernate regulator.

Figure 6-4. PSoC Power System

Note

The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as

shown in Figure 2-6.

You can power the device in internally regulated mode, where the voltage applied to the VDDx pins is as high as 5.5 V, and the internal

regulators provide the core voltages. In this mode, do not apply power to the V

CCx pins, and do not tie the VDDx pins to the VCCx

pins.

You can also power the device in externally regulated mode, that is, by directly powering the VCCD and VCCA pins. In this configuration,

the VDDD pins should be shorted to the VCCD pins and the VDDA pin should be shorted to the VCCA pin. The allowed supply range in

this configuration is 1.71 V to 1.89 V. After power up in this configuration, the internal regulators are on by default, and should be

disabled to reduce power consumption.

VSSB

VDDIO0

VSSA

VCCA

VDDA

Digital

Regulators

Analog

Regulator

Analog

Domain

Digital

Domain

I2C

Regulator

Sleep

Regulator

Hibernate

Regulator

I/O Supply

VDDIO2

VDDIO0

VDDIO3

VDDIO1

0.1 µF

VDDD

1 µF

VDDA

0.1 µF

0.1µF

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