AD73322LAST datasheet(12/40 Pages) AD

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AD73322L

–12–

FB = 4kHz

FSINIT = DMCLK/8

a. Analog Antialias Filter Transfer Function

FB = 4kHz

FSINIT = DMCLK/8

NOISE TRANSFER FUNCTION

SIGNAL TRANSFER FUNCTION

b. Analog Sigma-Delta Modulator Transfer Function

FB = 4kHz

FSINTER = DMCLK/256

c. Digital Decimator Transfer Function

FB = 4kHz

FSINTER = DMCLK/256

FSFINAL = 8kHz

d. Final Filter LPF (HPF) Transfer Function

Figure 7. ADC Frequency Responses

Decimation Filter

The digital filter used in the AD73322L carries out two important

functions. Firstly, it removes the out-of-band quantization

noise, which is shaped by the analog modulator and secondly,

it decimates the high frequency bit stream to a lower rate 16-

bit word.

The antialiasing decimation filter is a sinc-cubed digital filter

that reduces the sampling rate from DMCLK/8 to DMCLK/256,

and increases the resolution from a single bit to 15 bits or greater

(depending on chosen sampling rate). Its Z transform is given as:

[(1 – Z

–N)/(1 – Z –1)]3

where N is set by the sampling rate (N = 32 @ 64 kHz sam-

pling. . . N = 256 @ 8 kHz sampling). Thus when the sampling

rate is 64 kHz, a minimal group delay of 25

µs can be achieved.

Word growth in the decimator is determined by the sampling

rate. At 64 kHz sampling, where the oversampling ratio between

sigma-delta modulator and decimator output equals 32, there

are five bits per stage of the three-stage Sinc3 filter. Due to symme-

try within the sigma-delta modulator, the LSB will always be a

zero; therefore, the 16-bit ADC output word will have 2 LSBs

equal to zero, one due to the sigma-delta symmetry and the

other being a padding zero to make up the 16-bit word. At

lower sampling rates, decimator word growth will be greater

than the 16-bit sample word, therefore truncation occurs in

transferring the decimator output as the ADC word. For example,

at 8 kHz sampling, word growth reaches 24 bits due to the OSR

of 256 between sigma-delta modulator and decimator output.

This yields eight bits per stage of the three-stage Sinc3 filter.

ADC Coding

The ADC coding scheme is in twos complement format (see

Figure 8). The output words are formed by the decimation

filter, which grows the word length from the single-bit output

of the sigma-delta modulator to a word length of up to 24 bits

(depending on decimation rate chosen), which is the final out-

put of the ADC block. In Data Mode this value is truncated to

16 bits for output on the Serial Data Output (SDO) pin.

VREF + (VREF

0.32875)

VREF

VREF – (VREF

0.32875)

10...00

00...00

01...11

ADC CODE DIFFERENTIAL

ANALOG

INPUT

VINN

VINP

VREF + (VREF

0.6575)

VREF – (VREF

0.6575)

10...00

00...00

01...11

ADC CODE SINGLE-ENDED

ANALOG

INPUT

VINP

VINN

Figure 8. ADC Transfer Function

In mixed Control/Data Mode, the resolution is fixed at 15 bits,

with the MSB of the 16-bit transfer being used as a flag bit to

indicate either control or data in the frame.

Decoder Channel

The decoder channels consist of digital interpolators, digital

sigma-delta modulators, single-bit digital-to-analog converters

(DAC), analog smoothing filters and programmable gain ampli-

fiers with differential outputs.

DAC Coding

The DAC coding scheme is in twos complement format with

0x7FFF being full-scale positive and 0x8000 being full-

scale negative.

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