AD73322LAST datasheet(15/40 Pages) AD

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AD73322L

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In both transmit and receive modes, data is transferred at the

serial clock (SCLK) rate with the MSB being transferred first.

Due to the fact that the SPORT of each codec block uses a com-

mon serial register for serial input and output, communications

between an AD73322L codec and a host processor (DSP engine)

must always be initiated by the codecs themselves. In this con-

figuration the codecs are described as being in Master mode.

This ensures that there is no collision between input data and

output samples.

SPORT Overview

The AD73322L SPORT is a flexible, full-duplex, synchronous

serial port whose protocol has been designed to allow up to four

AD73322L devices (or combinations of AD73322L dual codecs

and AD73311 single codecs up to eight codec blocks) to be con-

nected, in cascade, to a single DSP via a six-wire interface. It has a

very flexible architecture that can be configured by programming

two of the internal control registers in each codec block. The

AD73322L SPORT has three distinct modes of operation: Control

Mode, Data Mode and Mixed Control/Data Mode.

NOTE: As each codec has its own SPORT section, the register

settings in both SPORTs must be programmed. The registers

that control SPORT and sample rate operation (CRA and CRB)

must be programmed with the same values, otherwise incorrect

operation may occur.

In Control Mode (CRA:0 = 0), the device’s internal configura-

tion can be programmed by writing to the eight internal control

registers. In this mode, control information can be written to or

read from the codec. In Data Mode (CRA:0 = 1), (CRA:1 = 0),

information sent to the device is used to update the decoder

section (DAC), while the encoder section (ADC) data is read

from the device. In this mode, only DAC and ADC data is

written to or read from the device. Mixed mode (CRA:0 = 1

and CRA:1 = 1) allows the user to choose whether the informa-

tion being sent to the device contains either control information

or DAC data. This is achieved by using the MSB of the 16-bit

frame as a flag bit. Mixed mode reduces the resolution to 15 bits

with the MSB being used to indicate whether the information in

the 16-bit frame is control information or DAC/ADC data.

The SPORT features a single 16-bit serial register that is used

for both input and output data transfers. As the input and out-

put data must share the same register, some precautions must be

observed. The primary precaution is that no information must

be written to the SPORT without reference to an output sample

event, which is when the serial register will be overwritten with

the latest ADC sample word. Once the SPORT starts to output

the latest ADC word, it is safe for the DSP to write new control

or data words to the codec. In certain configurations, data can

be written to the device to coincide with the output sample being

shifted out of the serial register—see section on interfacing devices.

The serial clock rate (CRB:2–3) defines how many 16-bit words

can be written to a device before the next output sample event

will happen.

The SPORT block diagram shown in Figure 10 details the

blocks associated with Codecs 1 and 2, including the eight

control registers (A–H), external MCLK to internal DMCLK

divider and serial clock divider. The divider rates are controlled

by the setting of Control Register B. The AD73322L features a

master clock divider that allows users the flexibility of dividing

externally available high frequency DSP or CPU clocks to gen-

erate a lower frequency master clock internally in the codec,

which may be more suitable for either serial transfer or sampling

rate requirements. The master clock divider has five divider

options (

÷ 1 default condition, ÷ 2, ÷ 3, ÷ 4, ÷ 5) that are set by

loading the master clock divider field in Register B with the

appropriate code (see Table VII). Once the internal device master

clock (DMCLK) has been set using the master clock divider, the

sample rate and serial clock settings are derived from DMCLK.

The SPORT can work at four different serial clock (SCLK)

rates: chosen from DMCLK, DMCLK/2, DMCLK/4 or

DMCLK/8, where DMCLK is the internal or device master

clock resulting from the external or pin master clock being

divided by the master clock divider.

SPORT Register Maps

There are two register banks for each codec in the AD73322L:

the control register bank and the data register bank. The con-

trol register bank consists of eight read/write registers, each

eight bits wide. Table XI shows the control register map for

the AD73322L. The first two control registers, CRA and CRB,

are reserved for controlling the SPORT. They hold settings for

parameters such as serial clock rate, internal master clock rate,

sample rate and device count. As both codecs are internally

cascaded, registers CRA and CRB on each codec must be pro-

grammed with the same setting to ensure correct operation (this

is shown in the programming examples). The other five registers;

CRC through CRH are used to hold control settings for the

ADC, DAC, Reference, Power Control and Gain Tap sections

of the device. It is not necessary that the contents of CRC

through CRH on each codec be similar. Control registers are

written to on the negative edge of SCLK. The data register

bank consists of two 16-bit registers that are the DAC and

ADC registers.

Master Clock Divider

The AD73322L features a programmable master clock divider

that allows the user to reduce an externally available master

clock, at pin MCLK, by one of the ratios 1, 2, 3, 4 or 5 to pro-

duce an internal master clock signal (DMCLK) that is used to

calculate the sampling and serial clock rates. The master clock

divider is programmable by setting CRB:4-6. Table VII shows

the division ratio corresponding to the various bit settings. The

default divider ratio is divide-by-one.

Table VII. DMCLK (Internal) Rate Divider Settings

MCD2

MCD1

MCD0

DMCLK Rate

MCLK

MCLK/2

MCLK/3

MCLK/4

MCLK/5

MCLK

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