AD73322LAST datasheet(24/40 Pages) AD

24 / 40 page

REV. 0

AD73322L

–24–

Table XXI. Device Count Settings

DC2

DC1

DC0

Cascade Length

PERFORMANCE

As the AD73322L is designed to provide high performance, low

cost conversion, it is important to understand the means by

which this high performance can be achieved in a typical appli-

cation. This section will, by means of spectral graphs, outline

the typical performance of the device and highlight some of the

options available to users in achieving their desired sample rate,

either directly in the device or by doing some post-processing in

the DSP, while also showing the advantages and disadvantages

of the different approaches.

Encoder Section

The AD73322L offers a variable sampling rate from a fixed

MCLK frequency—with 64 kHz, 32 kHz, 16 kHz and 8 kHz

being available with a 16.384 MHz external clock. Each of these

sampling rates preserves the same sampling rate in the ADC’s

sigma-delta modulator, which ensures that the noise perfor-

mance is optimized in each case. The examples below will show

the performance of a 1 kHz sine wave when converted at the

various sample rates.

The range of sampling rates is aimed to offer the user a degree

of flexibility in deciding how their analog front end is to be

implemented. The high sample rates of 64 kHz and 32 kHz are

suited to those applications, such as active control, where low

conversion group delay is essential. On the other hand, the lower

sample rates of 16 kHz and 8 kHz are better suited for appli-

cations such as telephony, where the lower sample rates result

in lower DSP overhead.

Figure 20 shows the spectrum of the 1 kHz test tone sampled at

64 kHz. The plot shows the characteristic shaped noise floor of

a sigma-delta converter, which is initially flat in the band of

interest but then rises with increasing frequency. If a suitable

digital filter is applied to this spectrum, it is possible to eliminate

the noise floor in the higher frequencies. This signal can then be

used in DSP algorithms or can be further processed in a deci-

mation algorithm to reduce the effective sample rate. Figure 17

shows the resulting spectrum following the filtering and decima-

tion of the spectrum of Figure 16 from 64 kHz to an 8 kHz rate.

FREQUENCY – Hz

0.5

–20

1.0

1.5

2.0

2.5

3.0

3.5

–100

–140

–120

–40

–60

–80

104

Figure 16. FFT (ADC 64 kHz Sampling)

FREQUENCY – Hz

500

–20

–40

–60

–80

–100

–120

1000

1500

2000

2500

3000

3500

4000

Figure 17. FFT (ADC 8 kHz Filtered and Decimated from

64 kHz)

The AD73322L also features direct sampling at the lower rate

of 8 kHz. This is achieved by the use of extended decimation

registers within the decimator block, which allows for the

increased word growth associated with the higher effective

oversampling ratio. Figure 18 details the spectrum of a 1 kHz

test tone converted at an 8 kHz rate.

FREQUENCY – Hz

500

100

1000

1500

2000

2500

3000

3500

4000

150

Figure 18. FFT (ADC 8 kHz Direct Sampling)

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