AD73322LAST datasheet(16/40 Pages) AD

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AD73322L

–16–

Serial Clock Rate Divider

The AD73322L features a programmable serial clock divider

that allows users to match the serial clock (SCLK) rate of the

data to that of the DSP engine or host processor. The maximum

SCLK rate available is DMCLK and the other available rates

are: DMCLK/2, DMCLK/4 and DMCLK/8. The slowest rate

(DMCLK/8) is the default SCLK rate. The serial clock divider

is programmable by setting bits CRB:2–3. Table VIII shows the

serial clock rate corresponding to the various bit settings.

Table VIII. SCLK Rate Divider Settings

SCD1

SCD0

SCLK Rate

DMCLK/8

DMCLK/4

DMCLK/2

DMCLK

Sample Rate Divider

The AD73322L features a programmable sample rate divider

that allows users flexibility in matching the codec’s ADC and

DAC sample rates (decimation/interpolation rates) to the needs

of the DSP software. The maximum sample rate available is

DMCLK/256, which offers the lowest conversion group delay,

while the other available rates are: DMCLK/512, DMCLK/

1024 and DMCLK/2048. The slowest rate (DMCLK/2048) is

the default sample rate. The sample rate divider is program-

mable by setting bits CRB:0-1. Table IX shows the sample

rate corresponding to the various bit settings.

Table IX. Sample Rate Divider Settings

DIR1

DIR0

SCLK Rate

DMCLK/2048

DMCLK/1024

DMCLK/512

DMCLK/256

DAC Advance Register

The loading of the DAC is internally synchronized with the

unloading of the ADC data in each sampling interval. The

default DAC load event happens one SCLK cycle before the

SDOFS flag is raised by the ADC data being ready. However,

this DAC load position can be advanced before this time by

modifying the contents of the DAC advance field in Control

increments of weight 1/(FS

× 32); see Table X. The sample rate

FS is dependent on the setting of both the MCLK divider and

the Sample Rate divider; see Tables VII and IX. In certain cir-

cumstances this DAC update adjustment can reduce the group

delay when the ADC and DAC are used to process data in series.

Appendix C details how the DAC advance feature can be used.

NOTE: The DAC advance register should not be changed while

the DAC section is powered up.

Table X. DAC Timing Control

DA4

DA3

DA2

DA1

DA0

Time Advance

000 s

1/(FS

× 32) s

2/(FS

× 32) s

30/(FS

× 32) s

31/(FS

× 32) s

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