AD73322LAST datasheet(14/40 Pages) AD

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AD73322L

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Analog Gain Tap

The analog gain tap is configured as a programmable differential

amplifier whose input is taken from the ADC’s input signal

path. The output of the analog gain tap is summed with the

output of the DAC. The gain is programmable using Control

with muting being achieved through a separate control setting

(Control Register F Bit 7). The gain increment per step is 0.0625.

The AGT is enabled by powering-up the AGT control bit in the

power control register (CRC:1). When this bit is set (=1) CRF

becomes an AGT control register with CRF:0-4 holding the

AGT coefficient, CRF:5 becomes an AGT enable and CRF:7

becomes an AGT mute control bit. Control bit CRF:5 connects/

disconnects the AGT output to the summer block at the output

of the DAC section while control bit CRF:7 overrides the gain

tap setting with a mute, (zero gain) setting. Table V shows the

gain versus digital setting for the AGT.

Table V. Analog Gain Tap Settings

AGTC4 AGTC3 AGTC2

AGTC1

AGTC0 Gain (dB)

+1.00

+0.9375

+0.875

+0.8125

+0.75

+0.0625

–0.0625

–0.875

–0.9375

–1.00

*AGT and DGT weights are given for the case of VFBNx (connected to the

sigma-delta modulator’s positive input) being at a higher potential than VFBPx

(connected to the sigma-delta modulator’s negative input).

Digital Gain Tap

The digital gain tap features a programmable gain block whose

input is taken from the bitstream output of the ADC’s sigma-

delta modulator. This single bit input (1 or 0) is used to add or

subtract a programmable value, which is the digital gain tap setting,

to the output of the DAC section’s interpolator. The program-

mable setting has 16-bit resolution and is programmed using the

settings in Control Registers G and H. (See Table VI).

Table VI. Digital Gain Tap Settings

DGT15–0 (Hex)

Gain

0x8000

–1.00

0x9000

–0.875

0xA000

–0.75

0xC000

–0.5

0xE000

–0.25

0x0000

0.00

0x2000

+0.25

0x4000

+0.05

0x6000

+0.75

0x7FFF

+0.99999

*AGT and DGT weights are given for the case of VFBNx (connected to the

sigma-delta modulator’s positive input) being at a higher potential than VFBPx

(connected to the sigma-delta modulator’s negative input).

Serial Port (SPORT)

The codecs communicate with a host processor via the bidirec-

tional synchronous serial port (SPORT), which is compatible

with most modern DSPs. The SPORT is used to transmit and

receive digital data and control information. The dual codec is

implemented using two separate codec blocks that are internally

cascaded with serial port access to the input of Codec1 and the

output of Codec2. This allows other single or dual codec devices to

be cascaded together (up to a limit of eight codec units).

MCLK

DIVIDER

MCLK

EXTERNAL

RESET

SDIFS

SDI

SERIAL PORT 1

(SPORT 1)

SERIAL REGISTER 1

SCLK

DIVIDER

SCLK

CONTROL

DMCLK INTERNAL

MCLK

DIVIDER

MCLK

EXTERNAL

RESET

SDIFS2

SDI2

SERIAL PORT 2

(SPORT 2)

SERIAL REGISTER 2

SCLK

DIVIDER

CONTROL

DMCLK INTERNAL

SDOFS

SDO

SDOFS1

SDO1

Figure 10. SPORT Block Diagram

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