ADV7191 datasheet(49/69 Pages) AD

49 / 69 page

ADV7190/ADV7191

–49–

REV. 0

Time, tPD, is the time needed by the ADV7190/ADV7191 to

interpolate input data on TTX and insert it onto the CVBS

or Y outputs, such that it appears tSYNTTXOUT = 10.2

µs after the

leading edge of the horizontal signal. Time, TTXDEL, is the pipe-

line delay time by the source that is gated by the TTXREQ signal

in order to deliver TTX data.

With the programmability that is offered with TTXREQ signal

on the Rising/Falling edges, the TTX data is always inserted at

the correct position of 10.2

µs after the leading edge of Horizontal

Sync pulse, which enables a source interface with variable pipe-

line delays.

The width of the TTXREQ signal must always be maintained

so it allows the insertion of 360 (in order to comply with the

Teletext Standard PAL-WST) teletext bits at a text data rate of

6.9375 Mbits/s. This is achieved by setting TC03–TC00 to 0.

The insertion window is not open if the Teletext Enable bit

(MR34) is set to 0.

APPENDIX 5

TELETEXT INSERTION

Teletext Protocol

The relationship between the TTX bit clock (6.9375 MHz) and

the system CLOCK (27 MHz) for 50 Hz is given as follows:

(27 MHz/4) = 6.75 MHz

(6.9375

× 106/6.75 × 106 = 1.027777

Thus 37 TTX bits correspond to 144 clocks (27 MHz), each bit

has a width of almost four clock cycles. The ADV7190/ADV7191

uses an internal sequencer and variable phase interpolation ﬁlter

to minimize the phase jitter and thus generate a bandlimited

signal which can be output on the CVBS and Y outputs.

At the TTX input the bit duration scheme repeats after every

37 TTX bits or 144 clock cycles. The protocol requires that

TTX Bits 10, 19, 28, 37 are carried by three clock cycles, all

other bits by four clock cycles. After 37 TTX bits, the next bits

with three clock cycles are Bits 47, 56, 65, and 74. This scheme

holds for all following cycles of 37 TTX bits, until all 360 TTX

bits are completed. All teletext lines are implemented in the

same way. Individual control of teletext lines are controlled

by Teletext Setup Registers.

ADDRESS & DATA

RUN-IN CLOCK

TELETEXT VBI LINE

45 BYTES (360 BITS) – PAL

Figure 92. Teletext VBI Line

PROGRAMMABLE PULSE EDGES

tPD

CVBS/Y

HSYNC

TTXREQ

TTXDATA

tSYNTTXOUT = 10.2 s

tPD = PIPELINE DELAY THROUGH ADV7190/ADV7191

TTXDEL = TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])

TTXDEL

TTXST

tSYNTTXOUT

10.2 s

Figure 93. Teletext Functionality Diagram

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