ADV7191 datasheet(34/69 Pages) AD

34 / 69 page

ADV7190/ADV7191

–34–

REV. 0

Reserved (MR76)

A Logic 0 must be written to this bit.

CLAMP/

VSO Select (MR77)

This bit is used to select the functionality of Pin 51. A 1 selects

CLAMP as the output signal. A 0 selects

VSO output.

MODE REGISTER 8

MR8 (MR87–MR80)

(Address (SR4–SR0) = 08H)

Mode Register 8 is an 8-bit-wide register. Figure 58 shows the

various operations under the control of Mode Register 8.

MR8 BIT DESCRIPTION

Reserved (MR80, MR81)

A Logic 0 must be written to these bits.

Double Buffer Control (MR82)

Double buffering can be enabled or disabled on the Contrast

Control Register, U Scale Register, V Scale Register, Hue Adjust

Control Register, Closed Captioning Register, Brightness Con-

trol Register, Gamma Curve Select Bit and the Macrovision

Registers. Double Buffering is not available in Master Timing

mode.

16-Bit Pixel Port (MR83)

This bit controls if the ADV7190/ADV7191 accepts 8-bit or

16-bit input data. In 8-bit mode the data will be input on Pins

P0–P7. Unused pixel inputs should be grounded.

Reserved (MR84)

A Logic 0 must be written to this bit.

DNR Enable Control (MR85)

To enable the DNR process this bit has to be set to 1. If this bit

is set to 0, the DNR processing is bypassed. For further infor-

mation on DNR controls see DNR Registers 2–0, DNR1 Bit

Description, and DNR2 Bit Description sections.

Gamma Enable Control (MR86)

To enable the programmable gamma correction this bit has

to be set to enabled (MR86 is set to 1). For further information

on Gamma Correction controls see Gamma Correction Registers

0–13 (Gamma 0–13) (Address (SR5–SR0) = 26H–32H section.

Gamma Curve Select Control (MR87)

This bit selects which of the two programmable gamma curves is

used. When setting MR87 to 0, the gamma correction curve to be

processed is Curve A. Otherwise, Curve B is selected. For fur-

ther information on Gamma Correction controls see Gamma

Correction Registers 0–13 (Gamma 0–13) (Address (SR5–SR0)

= 26H–32H section.

MODE REGISTER 9

MR9 (MR97–MR90)

(Address (SR4–SR0) = 09H)

Mode Register 9 is an 8-bit-wide register. Figure 59 shows

the various operations under the control of Mode Register 9.

MR9 BIT DESCRIPTION

Undershoot Limiter (MR90–MR91)

This control ensures that no luma video data will go below a

programmable level. This prevents any synchronization problems

due to luma signals going below the blanking level. Available

limit levels are –1.5 IRE, –6 IRE, –11 IRE.

Note that this facility is only available in 4

× Oversampling mode

(MR16 = 1). When the device is operated in 2

× Oversampling

mode (MR16 = 0) or RGB outputs without RGB sync are

selected, the minimum luma level is set in Timing Register 0,

TR06 (Min Luma Control).

Reserved (MR92–MR93)

A Logic 0 must be written to these bits.

Chroma Delay Control (MR94–MR95)

The Chroma Signal can be delayed by up to 296 ns (eight clock

cycles at 27 MHz) using MR94–MR95. For further informa-

tion see also Chroma/Luma Delay section.

Reserved (MR96–MR97)

A Logic 0 must be written to these bits.

ZERO MUST

BE WRITTEN

TO THIS BIT

MR84

MR87

MR86

MR85

MR84

MR83

MR82

MR81

MR80

8-BIT PIXEL PORT

16-BIT PIXEL PORT

MR83

16-PIXEL PORT

DNR ENABLE

CONTROL

MR85

DISABLE

ENABLE

DISABLE

ENABLE

MR82

DOUBLE BUFFER

CONTROL

ZERO MUST

BE WRITTEN

TO THESE BITS

MR81 MR80

DISABLE

ENABLE

MR86

GAMMA ENABLE

CONTROL

CURVE A

CURVE B

MR87

GAMMA CURVE

SELECT CONTROL

Figure 58. Mode Register 8 (MR8)

MR97

MR96

MR95

MR94

MR93

MR92

MR91

MR90

ZERO MUST

BE WRITTEN

TO THESE BITS

MR93 MR92

ZERO MUST

BE WRITTEN

TO THESE BITS

MR97 MR96

CHROMA

DELAY CONTROL

MR95 MR94

0ns DELAY

148ns DELAY

296ns DELAY

RESERVED

UNDERSHOOT

LIMITER

MR91 MR90

DISABLED

–11 IRE

–6 IRE

–1.5 IRE

Figure 59. Mode Register 9 (MR9)

ADV7191 Datasheet(PDF) 34 Page - Analog Devices

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