ADV7191 datasheet(30/69 Pages) AD

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ADV7190/ADV7191

–30–

REV. 0

MODE REGISTER 2

MR2 (MR27–MR20)

(Address (SR4–SR0) = 02H)

Mode Register 2 is a 8-bit wide register.

Figure 52 shows the various operations under the control of Mode

MR2 BIT DESCRIPTION— RGB/YUV Control (MR20)

This bit enables the output from the small or large DACs to be

set to YUV or RGB output video standard.

DAC Output Control (MR21)

This bit controls the output from DACs A, B, and C. When this

bit is set to 1, Composite, Luma, and Chroma Signals are out-

put from DACs A, B, and C (respectively). When this bit is set

to 0, RGB or YUV may be output from these DACs.

SCART Enable Control (MR22)

This bit is used to switch the DAC outputs from SCART to a

EUROSCART conﬁguration. A complete table of all DAC out-

put conﬁgurations is shown in Table III.

Pedestal Control (MR23)

This bit speciﬁes whether a pedestal is to be generated on the

NTSC composite video signal. This bit is invalid when the device

is conﬁgured in PAL mode.

Square Pixel Control (MR24)

This bit is used to set up square pixel mode. This is available in

Slave Mode only. For NTSC, a 24.5454 MHz clock must be

supplied. For PAL, a 29.5 MHz clock must be supplied. Square

pixel operation is not available in 4

× Oversampling mode.

Standard I

2C Control (MR25)

This bit controls the video standard used by the ADV7190/

ADV7191. When this bit is set to 1 the video standard as pro-

grammed in Output Video Standard Selection (MR00, MR01).

When MR25 is set to 0, the ADV7190/ADV7191 is forced into

the standard selected by the NTSC_PAL pin. When NTSC_PAL

is low the standard is NTSC, when the NTSC_PAL pin is high,

the standard is PAL.

Pixel Data Valid Control (MR26)

After resetting the device, this bit has the value 0 and the pixel

data input to the encoder is blanked such that a black screen is

output from the DACs. The ADV7190/ADV7191 will be set

to Master Mode timing. When this bit is set to 1 by the user

(via the I

2C), pixel data passes to the pins and the encoder re-

verts to the Timing Mode deﬁned by Timing Register 0.

Sleep Mode Control (MR27)

When this bit is set (1), Sleep Mode is enabled. With this mode

enabled, the ADV7190/ADV7191 current consumption is reduced

to less than 1 mA. The I

2C registers can be written to and read

from when the ADV7190/ADV7191 is in Sleep Mode.

When the device is in Sleep Mode and 0 is written to MR27, the

ADV7190/ADV7191 will come out of Sleep Mode and resume

normal operation. Also, if a

RESET is applied during Sleep

Mode, the ADV7190/ADV7191 will come out of Sleep Mode

and resume normal operation.

For this to operate, Power Up in Sleep Mode Control has to be

enabled (MR60 = 0), otherwise Sleep Mode is controlled by

the PAL_NTSC and SCRESET/RTC/TR pins.

Table III. DAC Output Conﬁguration Matrix

SCART

DAC O/P

RGB/YUV

MR22

MR21

MR20

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

CVBS

LUMA

CHROMA

CVBS

LUMA

CHROMA

CVBS

LUMA

CHROMA

CVBS

LUMA

CHROMA

CVBS

LUMA

CHROMA

CVBS

LUMA

CHROMA

CVBS

LUMA

CHROMA

CVBS

LUMA

CHROMA

MR27

MR26

MR25

MR24

MR23

MR22

MR21

MR20

RGB/YUV

CONTROL

RGB OUTPUT

YUV OUTPUT

MR20

SCART ENABLE

CONTROL

DISABLE

ENABLE

MR22

SQUARE PIXEL

CONTROL

DISABLE

ENABLE

MR24

PIXEL DATA

VALID CONTROL

DISABLE

ENABLE

MR26

DAC OUTPUT

CONTROL

RGB/YUV/COMP

COMP/LUMA/CHROMA

MR21

PEDESTAL

CONTROL

PEDESTAL OFF

PEDESTAL ON

MR23

STANDARD I2C

CONTROL

DISABLE

ENABLE

MR25

SLEEP MODE

CONTROL

DISABLE

ENABLE

MR27

Figure 52. Mode Register 2 (MR2)

ADV7191 Datasheet(PDF) 30 Page - Analog Devices

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