ADV7191 datasheet(18/69 Pages) AD

18 / 69 page

ADV7190/ADV7191

–18–

REV. 0

In DNR Mode, if the absolute value of the ﬁlter output is smaller

than the threshold, it is assumed to be noise. A programmable

amount (Coring Gain Control) of this noise signal will be sub-

tracted from the original signal.

In DNR Sharpness Mode, if the absolute value of the ﬁlter output

is less than the programmed threshold, it is assumed to be noise,

as before. Otherwise, if the level exceeds the threshold, now

being identiﬁed as a valid signal, a fraction of the signal (Coring

Gain Control) will be added to the original signal in order to boost

high frequency components and to sharpen the video image.

In MPEG systems it is common to process the video information

in blocks of 8

× 8 pixels for MPEG2 systems, or 16 × 16 pixels for

MPEG1 systems (Block Size Control). DNR can be applied to

the resulting block transition areas that are known to contain

noise. Generally the block transition area contains two pixels.

It is possible to deﬁne this area to contain four pixels (Border

Area Control).

It is also possible to compensate for variable block positioning or

differences in YCrCb pixel timing with the use of the (Block Offset

Control). See Figure 82 for further information (Mode Register

8, DNR Registers 0–2.)

DOUBLE BUFFERING

Double buffering can be enabled or disabled on the following

registers: Closed Captioning Registers, Brightness Control,

V Scale, U Scale, Contrast Control, Hue Adjust, the Gamma

Curve Select bit, and Macrovision Registers. These registers are

updated once per ﬁeld on the falling edge of the

VSYNC signal.

Double buffering improves the overall performance of the

ADV7190/ADV7191, since modiﬁcations to register settings

will not be made during active video, but take effect on the

start of the active video. (Mode Register 8.)

GAMMA CORRECTION CONTROL

Gamma correction may be performed on the luma data. The

user has the choice to use either of two different gamma curves,

A or B. At any one time one of these curves is operational if

gamma correction is enabled. Gamma correction allows the

mapping of the luma data to a user-deﬁned function. (See Gamma

Correction Registers 0–13 section.) (Mode Register 8, Gamma

Correction Registers 0–13.)

NTSC PEDESTAL CONTROL

In NTSC mode it is possible to have the pedestal signal gener-

ated on the output video signal. (Mode Register 2.)

POWER-ON

RESET

After power-up, it is necessary to execute a

RESET operation. A

reset occurs on the falling edge of a high-to-low transition on the

RESET pin. This initializes the pixel port such that the data on

the pixel inputs pins is ignored. See Appendix 8 for the register

settings after

RESET is applied.

REAL-TIME CONTROL, SUBCARRIER RESET, AND

TIMING RESET

Together with the SCRESET/RTC/TR pin and of Mode

be used in (a) Timing Reset Mode, (b) Subcarrier Phase

Reset Mode or (c) RTC Mode.

(a) A TIMING RESET is achieved in holding this pin high. In

this state the horizontal and vertical counters will remain reset.

On releasing this pin (set to low), the internal counters will

commence counting again. The minimum time the pin has

to be held high is 37 ns (1 clock cycle at 27 MHz), otherwise

the reset signal might not be recognized.

(b) The SUBCARRIER PHASE will reset to that of Field 0 at

the start of the following ﬁeld when a low-to-high transition

occurs on this input pin.

lock to an external video source.

The real-time control mode allows the ADV7190/ADV7191

to automatically alter the subcarrier frequency to compen-

sate for line length variations. When the part is connected to

a device that outputs a digital datastream in the RTC format

such as an ADV7185 video decoder (see Figure 32), the part

will automatically change to the compensated subcarrier

frequency on a line-by-line basis. This digital datastream is

67 bits wide and the subcarrier is contained in Bits 0 to 21.

Each bit is two clock cycles long. 00Hex should be written

into all four Subcarrier Frequency registers when using this

mode. (Mode Register 4.)

SCH PHASE MODE

The SCH phase is conﬁgured in default mode to reset every

four (NTSC) or eight (PAL) ﬁelds to avoid an accumulation of

SCH phase error over time. In an ideal system, zero SCH phase

error would be maintained forever, but in reality, this is impos-

sible to achieve due to clock frequency variations. This effect is

reduced by the use of a 32-bit DDS, which generates this SCH.

Resetting the SCH phase every four or eight ﬁelds avoids the

accumulation of SCH phase error, and results in very minor SCH

phase jumps at the start of the four or eight ﬁeld sequence.

Automatically resetting the SCH phase should not be done if

the video source does not have stable timing or the ADV7190/

ADV7191 is conﬁgured in RTC mode. Under these conditions

(unstable video) the Subcarrier Phase Reset should be en-

abled but no reset applied. In this conﬁguration the SCH

Phase will never be reset; this means that the output video will

now track the unstable input video.

The Subcarrier Phase Reset, when applied, will reset the SCH

phase to Field 0 at the start of the next ﬁeld (e.g., Subcarrier

Phase Reset applied in Field 5 (PAL) on the start of the next

ﬁeld SCH phase will be reset to Field 0). (Mode Register 4.)

SLEEP MODE

If, after

RESET, the SCRESET/RTC/TR and NTSC_PAL pins

are both set high, the ADV7190/ADV7191 will power-up in

Sleep Mode to facilitate low power consumption before all

registers have been initialized. If Power-Up in Sleep Mode is

disabled, Sleep Mode control passes to the Sleep Mode control

in Mode Register 2 (i.e., control via I

2C). (Mode Register 2

and Mode Register 6.)

SQUARE PIXEL MODE

The ADV7190/ADV7191 can be used to operate in square pixel

mode. For NTSC operation an input clock of 24.5454 MHz is

required. Alternatively, for PAL operation, an input clock of

29.5 MHz is required. The internal timing logic adjusts ac-

cordingly for square pixel mode operation. Square pixel mode

is not available in 4

× Oversampling mode. (Mode Register 2.)

ADV7191 Datasheet(PDF) 18 Page - Analog Devices

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