ADV7191 datasheet(19/69 Pages) AD

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ADV7190/ADV7191

–19–

REV. 0

VERTICAL BLANKING DATA INSERTION AND

BLANK

INPUT

It is possible to allow encoding of incoming YCbCr data on

those lines of VBI that do not have line sync or pre-/post-

equalization pulses (see Figures 34 to 45). This mode of operation

is called Partial Blanking. It allows the insertion of any VBI

data (Opened VBI) into the encoded output waveform. This data

is present in digitized incoming YCbCr data stream (e.g., WSS

data, CGMS, VPS etc.). Alternatively, the entire VBI may be

blanked (no VBI data inserted) on these lines. VBI is available

in all timing modes.

The complete VBI is comprised of the following lines:

525/60 systems, Lines 525 to 21 for ﬁeld one and Lines 262 to

284 for ﬁeld two.

625/50 systems, Line 624 to Line 22 and Lines 311 to 335.

The Opened VBI consists of:

525/60 systems, Lines 10 to 21 for ﬁeld one and second half of

Lines 273 to 284 for ﬁeld two.

625/50 systems, Lines 7 to 22 and Lines 319 to 335. (Mode

It is possible to allow control over the

BLANK signal using

Timing Register 0. When the

BLANK input is enabled (TR03 =

0 and input pin tied low), the

BLANK input can be used to

input externally generated blank signals in Slave Mode 1, 2, or 3.

When the

BLANK input is disabled (TR03 = 1 and input pin

tied low or tied high), the

BLANK input is not used and the

ADV7190/ADV7191 automatically blanks all normally blank

lines as per CCIR-624. (Timing Register 0.)

YUV LEVELS

This functionality allows the ADV7190/ADV7191 to output

SMPTE levels or Betacam levels on the Y output when conﬁg-

ured in PAL or NTSC mode.

Sync

Video

Betacam

286 mV

714 mV

SMPTE

300 mV

700 mV

MII

300 mV

700 mV

As the data path is branched at the output of the ﬁlters the luma

signal relating to the CVBS or S-Video Y/C output is unaltered.

It is only the Y output of the YCrCb outputs that is scaled.

This control allows color component levels to have a peak-peak

amplitude of 700 mV, 1000 mV or the default values of 934 mV

in NTSC and 700 mV in PAL. (Mode Register 5.)

16-BIT INTERFACE

It is possible to input data in 16-bit format. In this case, the

interface only operates if the data is accompanied by separate

HSYNC/VSYNC/BLANK signals. Sixteen-bit mode is not avail-

able in Slave Mode 0 since EAV/SAV timing codes are used.

(Mode Register 8.)

OVERSAMPLING AND INTERNAL PLL

It is possible to operate all six DACs at 27 MHz (2

× Oversam-

pling) or 54 MHz (4

× Oversampling).

The ADV7190/ADV7191 is supplied with a 27 MHz clock synced

with the incoming data. Two options are available: to run the

device throughout at 27 MHz or to enable the PLL. In the latter

case, even if the incoming data runs at 27 MHz, 4

× Oversam-

pling and the internal PLL will output the data at 54 MHz.

NOTE

In 4

× Oversampling Mode the requirements for the optional

output ﬁlters are different from those in 2

× Oversampling. (Mode

27MHz

54MHz

OUTPUT

PLL

54MHz

ENCODER

ADV7190/ADV7191

PIXEL BUS

ENCODER

CORE

MPEG2

27.0

40.5

54.0

13.5

6.75

FILTER

REQUIREMENTS

FILTER

REQUIREMENTS

FREQUENCY – MHz

Figure 30. PLL and 4

× Oversampling Block Diagram

VIDEO TIMING DESCRIPTION

The ADV7190/ADV7191 is intended to interface to off-the-

shelf MPEG1 and MPEG2 Decoders. As a consequence, the

ADV7190/ADV7191 accepts 4:2:2 YCrCb Pixel Data via a

CCIR-656 Pixel Port and has several Video Timing Modes of

operation that allow it to be conﬁgured as either System Master

Video Timing Generator or a Slave to the System Video Timing

Generator. The ADV7190/ADV7191 generates all of the required

horizontal and vertical timing periods and levels for the analog

video outputs.

The ADV7190/ADV7191 calculates the width and placement of

analog sync pulses, blanking levels, and color burst envelopes.

Color bursts are disabled on appropriate lines and serration and

equalization pulses are inserted where required.

In addition, the ADV7190/ADV7191 supports a PAL or NTSC

square pixel operation. The part requires an input pixel clock of

24.5454 MHz for NTSC square pixel operation and an input

pixel clock of 29.5 MHz for PAL square pixel operation. The

internal horizontal line counters place the various video waveform

sections in the correct location for the new clock frequencies.

The ADV7190/ADV7191 has four distinct Master and four

distinct Slave timing conﬁgurations. Timing Control is estab-

lished with the bidirectional

HSYNC, BLANK, and VSYNC

pins. Timing Register 1 can also be used to vary the timing

pulsewidths and where they occur in relation to each other.

(Mode Register 2, Timing Register 0, 1.)

ADV7191 Datasheet(PDF) 19 Page - Analog Devices

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