SPRUG18 datasheet(122/214 Pages) TI

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TMS320C6474

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

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7.8.3.3

PLL Controller Divider 11 Register

The PLL controller divider 11 register (PLLDIV11) is shown in Figure 7-13 and described in Table 7-27.

Reserved

R-0

D11EN

Reserved

RATIO

R/W-1

R-0

R/W-3

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 7-13. PLL Controller Divider 11 Register (PLLDIV11) [Hex Address: 029A 017C]

Table 7-27. PLL Controller Divider 11 Register (PLLDIV11) Field Descriptions

Bit

Field

Value

Description

31:16

Reserved

Reserved. The reserved bit location is always read as 0. A value written to this field has no

effect.

D11EN

Divider 11 enable bit.

Divider 11 is disabled. No clock output.

Divider 11 is enabled.

14:5

Reserved

Reserved. The reserved bit location is always read as 0. A value written to this field has no

effect.

4:0

RATIO(1)

0-1Fh

Divider ratio bits.

0h-4h

Reserved, do not use.

7h-31h

÷8 to ÷ 32. Divide frequency by 8 to divide frequency by 32.

32h-1Fh

Reserved, do not use.

(1)

For more details, see SYSCLK11 description in Section 7.8.1.1.

122

Peripheral Information and Electrical Specifications

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