SPRUG18 datasheet(184/214 Pages) TI

184 / 214 page

GPIx

GPOx

TMS320C6474

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

www.ti.com

7.19 General Purpose Input/Output (GPIO)

On the C6474 device, the GPIO peripheral pins GP[11:0] are used to latch configuration pins. These pins

are sampled at power-on reset and are functional as GPIO pins the remainder of the time. For more

detailed information on device/peripheral configuration and the C6474 device pin muxing, see Section 3,

Device Configuration.

7.19.1 GPIO Peripheral Register Description(s)

Table 7-81. GPIO Registers

HEX ADDRESS

ACRONYM

02B0 0008

BINTEN

GPIO Interrupt per Bank Enable Register

02B0 000C

Reserved

02B0 0010

DIR

GPIO Direction Register

02B0 0014

OUT_DATA

GPIO Output Data Register

02B0 0018

SET_DATA

GPIO Set Data Register

02B0 001C

CLR_DATA

GPIO Clear Data Register

02B0 0020

IN_DATA

GPIO Input Data Register

02B0 0024

SET_RIS_TRIG

GPIO Set Rising Edge Interrupt Register

02B0 0028

CLR_RIS_TRIG

GPIO Clear Rising Edge Interrupt Register

02B0 002C

SET_FAL_TRIG

GPIO Set Falling Edge Interrupt Register

02B0 0030

CLR_FAL_TRIG

GPIO Clear Falling Edge Interrupt Register

02B0 008C

Reserved

02B0 0090 - 02B0 00FF

Reserved

02B0 0100 - 02B0 3FFF

Reserved

7.19.2 GPIO Electrical Data/Timing

Table 7-82. Timing Requirements for GPIO Inputs(1)

(see Figure 7-44)

NO.

PARAMETER

MIN

MAX

UNIT

tw(GPIH)

Pulse duration, GPIx high

12C - 3

tw(GPIL)

Pulse duration, GPIx low

12C - 3

(1)

C = 1/CPU CLK frequency, in ns.

Table 7-83. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs(1)

(see Figure 7-44)

NO.

PARAMETER

MIN

MAX

UNIT

tw(GPOH)

Pulse duration, GPOx high

36C - 8

tw(GPOL)

Pulse duration, GPOx low

36C - 8

(1)

C = 1/CPU CLK frequency, in ns.

Figure 7-44. GPIO Timing

184

Peripheral Information and Electrical Specifications

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