LBGA256 datasheet(83/153 Pages) NXP

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LPC4350_30_20_10

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Product data sheet

Rev. 4 — 26 March 2013

83 of 153

NXP Semiconductors

LPC4350/30/20/10

32-bit ARM Cortex-M4/M0 microcontroller

7.22.4 Internal RC oscillator (IRC)

The IRC is used as the clock source for the WWDT and/or as the clock that drives the

PLLs and the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 %

accuracy over the entire voltage and temperature range.

Upon power-up or any chip reset, the LPC4350/30/20/10 use the IRC as the clock source.

The boot loader then configures the PLL1 to provide a 96 MHz clock for the core and the

PLL0USB or PLL0AUDIO as needed if an external boot source is selected.

7.22.5 PLL0USB (for USB0)

PLL0 is a dedicated PLL for the USB0 High-speed controller.

PLL0 accepts an input clock frequency from an external oscillator in the range of 14 kHz

to 25 MHz. The input frequency is multiplied up to a high frequency with a Current

Controlled Oscillator (CCO). The CCO operates in the range of 4.3 MHz to 550 MHz.

7.22.6 PLL0AUDIO (for audio)

The audio PLL PLL0AUDIO is a general-purpose PLL with a small step size. This PLL

accepts an input clock frequency derived from an external oscillator or internal IRC. The

input frequency is multiplied up to a high frequency with a Current Controlled Oscillator

(CCO). A sigma-delta converter modulates the PLL divider ratios to obtain the desired

output frequency. The output frequency can be set as a multiple of the sampling frequency

fs to 32fs, 64fs, 128  fs, 256  fs, 384  fs, 512  fs and the sampling frequency fs can

range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48, 96,192) kHz. Many other

frequencies are possible as well using the integrated fractional divider.

7.22.7 System PLL1

The PLL1 accepts an input clock frequency from an external oscillator in the range of

10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current

Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO

operates in the range of 156 MHz to 320 MHz. This range is possible through an

additional divider in the loop to keep the CCO within its frequency range while the PLL is

providing the desired output frequency. The output divider can be set to divide by 2, 4, 8,

or 16 to produce the output clock. Since the minimum output divider value is 2, it is

insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed

following a chip reset. After reset, software can enable the PLL. The program must

configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a

clock source. The PLL settling time is 100

s.

7.22.8 Reset Generation Unit (RGU)

The RGU allows generation of independent reset signals for individual blocks and

peripherals on the LPC4350/30/20/10.

7.22.9 Power control

The LPC4350/30/20/10 feature several independent power domains to control power to

the core and the peripherals (see Figure 10). The RTC and its associated peripherals (the

alarm timer, the CREG block, the OTP controller, the back-up registers, and the event

router) are located in the RTC power-domain. The main regulator or a battery supply can

power the RTC. A power selector switch ensures that the RTC block is always powered

on.

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